Additional considerations
10.1 DIMM cooling and thermal stability
PDF · 83Page 83Check stability at operating temperature once thermal conditions have stabilized. A successful test immediately after a cold boot says nothing about memory behavior an hour later, after the DIMMs, PMIC, case air, and area around the CPU have warmed up.
The SPD Hub sensor is useful as a repeatable reference point, but it measures its own local temperature, not the hottest DRAM die. Some modules have no sensor at all. The trend for one kit and the temperature at the first error therefore matter more than someone else’s universal number.
THERMAL LOOP: RECORD THE ENTIRE CHAIN
WHAT TO RECORD DURING THE TEST
| Metric | Why it is needed | How to interpret it |
|---|---|---|
| SPD Hub Temperature | SPD Hub temperature of each module where a sensor is available | Watch Current and Maximum; compare identical sensors on the same test bench |
| VDD / VDDQ and RPM | Links heat to voltage and actual airflow | Higher voltage may reduce thermal margin even if POST becomes easier |
| Time to first error | Shows whether the error is related to warm-up | Repeat the same test with the same settings and different airflow |
| Case temperature | Distinguishes a cold test bench from a real scenario | Test the final profile in the normal closed case with heat from the GPU |
PRACTICAL SEQUENCE
1. COLD BASELINE
Start the selected test and record the initial temperature, VDD/VDDQ, fan speed, and system background load.
2. STEADY-STATE WARM-UP
Do not change conditions until the temperature plateaus; an early pass does not establish stability after warm-up.
3. REAL-WORLD WORST CASE
Repeat the workload in a closed case and, if typical for your use, with the graphics card warmed up.
4. DIAGNOSTIC AIRFLOW
With settings unchanged, direct airflow at the DIMMs. If the errors disappear, this indicates inadequate thermal margin, but it does not replace repeat testing.
10.2 Socket, mounting pressure, and IMC variation
PDF · 84Page 84The IMC (Integrated Memory Controller) is located in the CPU, and its signals pass through the LGA contacts, motherboard traces, and DIMM slots. A missing channel, a sharp deterioration in training after remounting, or instability on one channel therefore calls first for mechanical diagnosis at JEDEC settings, not additional voltage.
A contact frame changes socket geometry and pressure distribution. It may affect temperature and contact, but it does not improve the IMC’s intrinsic quality or guarantee a higher memory data rate.
SIGNAL PATH
ISOLATE THE PROBLEM BEFORE TRYING TO FIX IT
| Symptom | What to rule out | Action |
|---|---|---|
| A channel or DIMM is not detected | Module, slot, contamination, and socket contacts | One known-good DIMM in each recommended slot; then inspect the CPU and LGA |
| Training became worse after installing the cooler | Misalignment, tightening sequence, and tightening force | Return to the specified mounting procedure and retrain the memory completely |
| One channel is consistently weaker | Whether the error follows the module or the channel | Swap the DIMMs; repeat at JEDEC, then with the original profile |
| The frame lowered CPU temperature | Mistaking correlation for causation | Do not claim an IMC improvement without a repeatable increase in frequency or stability margin |
SAFE REINSTALLATION
1. JEDEC, THEN REMOVE POWER
Save the profile and test at JEDEC. Shut down the PC, switch off the power supply, and unplug the power cord; make sure standby power is gone.
2. INSPECT THE SEATING
Follow the motherboard’s ESD instructions; hold the CPU and DIMMs by the edges. With the motherboard horizontal, place the CPU without sliding it or touching the LGA contacts.
3. FOLLOW ONE MANUAL
Tighten the cooler or frame only in the sequence and to the force specified by its manufacturer; do not transfer torque values from other hardware.
4. RETRAIN AND RETEST
After any remounting, clear saved training and repeat cold-boot, warm-restart, and stress testing.
10.3 BIOS, MRC, and reproducibility
PDF · 85Page 85The BIOS version is part of the profile. An update may change MRC (Memory Reference Code, the memory-initialization code), CPU microcode, Intel ME, hidden Auto values, and Memory Fast Boot. Identical visible timings after a flash therefore do not guarantee the same training state.
For the Z790 Apex Encore, ASUS explicitly associates BIOS 2202 with the Intel IPU 2026.1 update and memory compatibility; ME changes at the same time, and its new version may remain after a BIOS rollback. Such a rollback does not always restore the previous software stack.
| Stage | What to do | What to record |
|---|---|---|
| Before flashing | Screenshots and manual records of every changed setting | BIOS, ME/CSME, microcode, MRC/Silicon Init, Memory Fast Boot, and trained values |
| Safe baseline | Return to a stable profile or JEDEC before flashing | Control run and absence of errors before the update |
| First boot | Reset to Defaults, JEDEC, and complete training | POST codes, training time, and values actually applied |
| Profile recovery | Enter settings manually; do not blindly load the old profile | Cold boot, warm restart, hot stress test, and sleep behavior |
| Comparison | Change only the BIOS while keeping hardware and conditions identical | If ME or microcode differs, mark the comparison as non-equivalent |
10.4 DATA INTEGRITY AND A SAFE ENVIRONMENT
PDF · 85Page 85Unstable memory is dangerous for more than blue screens: an error can enter an archive, project, file system, or synchronized folder without any obvious warning. An experimental profile must not operate on the only copy of important data.
| What to protect | Practical action | Verification |
|---|---|---|
| Important files | A 3-2-1 scheme, or at minimum a separate version on another medium/in the cloud | Open several files from the backup and know the restore procedure |
| OS and keys | Separate test installation/image; keep the BitLocker key off the test bench | Do not experiment in the only production environment |
| Firmware | Flash the BIOS only with known-stable memory and power | Do not update the BIOS on a marginal profile just to save one retraining cycle |
| Results | Store test logs, WHEA data, and settings outside a temporary folder | The last known-good point remains available after a failure |
10.5 Synthetic tests and real-world performance
PDF · 86Page 86AIDA64 and Intel MLC let you assess changes in memory bandwidth and latency, but their results do not directly indicate FPS gains, changes in frame time, or archiving speed. The real-world effect depends on the workload, CPU/GPU limit, working-set size, and background load.
THREE LEVELS OF MEASUREMENT
| Metric | What it shows | Main pitfall |
|---|---|---|
| Read / Write / Copy | Peak performance of the selected memory and cache path | The result depends on CPU/Ring frequencies, program version, and run conditions |
| Latency, ns | Synthetic end-to-end latency | Windows background activity, power state, and one lucky run can easily create a false win |
| Application score | Response of a specific algorithm to the entire platform | Does not let you attribute the entire gain to memory alone |
| 1% low / frametime | Rare slow frames and smoothness in a CPU-limited scene | Different programs calculate percentiles differently; use one methodology and several repeats |
10.6 DAILY, BENCHMARK, AND SCREENSHOT PROFILES
PDF · 86Page 8610.7 Four DIMMs and high capacities
PDF · 87Page 87Four modules, additional ranks, and higher electrical capacitance increase the load on the controller and signal path. Choose the configuration according to the required capacity: maximum frequency is a task for a 2-DIMM / 1SPC motherboard, while a 4-DIMM / 2SPC system requires a more moderate target and an exact QVL match.
Rank is determined by module organization, not by capacity alone. Two kits with the same gigabyte capacity can present different loads, so check the part number, rank count, and actual configuration of each DIMM.
| Configuration | Priority | Practical conclusion |
|---|---|---|
| 2 DIMM / 1DPC / 1R | Frequency and stability margin | Lowest load; best baseline for high-frequency overclocking |
| 2 DIMM / 1DPC / 2R | Capacity without a second branch | More ranks may mean a lower frequency, but there is still only one DIMM per channel |
| 4 DIMM / 2DPC / 1R | Capacity and availability | A second module per channel reduces electrical margin; two-DIMM XMP guarantees nothing |
| 4 DIMM / 2DPC / 2R | Maximum capacity | Heaviest load; begin at JEDEC and raise the frequency gradually |
| CUDIMM | Clean CK clock signal | CKD restores CK, but does not train DQ/DQS or eliminate the load of four modules |
LARGE-CAPACITY TUNING SEQUENCE
1. CHOOSE THE CAPACITY IN ADVANCE
Do not buy a second random kit later: even the same part number may receive a different IC revision.
2. CHECK THE QVL
Match the exact part number, module count, capacity, BIOS, and recommended slots.
3. START AT JEDEC
Verify that every channel and module works before enabling XMP or manual voltages.
4. LOWER THE DATA RATE BEFORE ADJUSTING VOLTAGE
If XMP is not repeatable, lower the frequency by one or two steps, then find the minimum voltages.
5. TUNE TIMINGS AFTER FREQUENCY
First stabilize training and booting, then tighten the timings in small groups.
6. VALIDATE EVERY MODE
Several cold boots and warm restarts, a hot memory test, and a normal workload.
10.8 Reference materials for reproducing a configuration
PDF · 88Page 88To reproduce a profile, save its settings, test conditions and results. The materials must make it possible to reconstruct the test bench a month later and understand changes after a BIOS update, remount, or module replacement.
| Material | What must be visible | Why |
|---|---|---|
| Platform record | CPU-Z CPU/Mainboard, BIOS, microcode, and Windows version | Distinguishes the profile from another firmware version and CPU sample |
| Memory + SPD | Frequency, Gear, primary timings, and every occupied SPD slot | Confirms the active mode and exact modules |
| Complete timings | ASRock Timing Configurator or MemTweakIt after boot | Shows the runtime values actually applied. |
| Sensors | HWiNFO Current/Minimum/Maximum: DIMM, VDD/VDDQ telemetry, CPU/Ring, WHEA | Records conditions, temperature, and logged WHEA events. |
| BIOS profile | File on USB plus screenshots of every changed page | The file may be incompatible with another version; screenshots remain readable |
| Tests and booting | Version, config, duration, result, cold/warm boot | Lets others repeat the test instead of merely trusting the word ‘stable’ |
10.9 SOURCES, LIMITS OF EVIDENCE, AND CHANGE LOG
PDF · 88Page 88| Level | Basis | How we use it |
|---|---|---|
| A | Datasheet, Intel/JEDEC, manual, QVL, and release notes | Record what the manufacturer actually stated for the specific version |
| B | Repeatable A/B test on the described system | Practical conclusion with conditions, multiple runs, and original logs |
| C | Several independent community results | A starting point for a hypothesis; not a universal rule or substitute for your own testing |
| D | Single screenshot or retelling | Only a reason to investigate; without the platform and methodology, it is not used as evidence |
MINIMUM ENTRY IN THE REVISION LOG
- Date, document revision number, and changed section.
- Previous claim, new claim, and reason for the change.
- Primary source or link to a reproducible test.
- Platform, BIOS, DIMM capacity/rank, and test conditions.
- Whether previously published profiles must be retested.