Formulas
DDR5/BL16 without CRC. Examples: 8200 MT/s, CL36/CWL34. Values are in cycles; overclocking guidelines.
PRIMARY TIMINGS
tCWL = tCL − 2 = 34; tCL, ns = tCL × 2000 / MT/s ≈ 8.78 ns.
tRAS = tRCD(RD) + tRTP - guideline for an early read; tRC = tRAS + tRP.
SECONDARY TIMINGS
tWR = 48 - the overclocking standard used in this manual; do not reduce it further.
tRTP = 12; do not go lower: this is the minimum MR6 code. At high data rates, stability may require tRTP = 14.
tFAW, 1 KB (x8): 4 × tRRD_S = 4 × 8 = 32.
tFAW, 2 KB (x16): the greater of 4 × tRRD_S and 40 = 40 with RRD_S8.
tRFCpb ≈ tRFC − 30 × MT/s / 2000: at 8200, 688 − 123 = 565. Hynix/FGR estimate, where tRFC means tRFC2; do not calculate this from tRFC1. tRFC, cycles = tRFC, ns × MT/s / 2000; round up. I leave tRFCpb on Auto and do not tune it manually.
TERTIARY TIMINGS: BASE CALCULATION AND UTILITY READOUTS
| Parameter | DDR5 calculation* | Old DDR4-burst calculation |
|---|---|---|
| tWTR_L | = tWRRD_sg − tCWL − 10 | = tWRRD_sg − tCWL − 6 |
| tWTR_S | = tWRRD_dg − tCWL − 10 | = tWRRD_dg − tCWL − 6 |
| tWR | = tWRPRE − tCWL − 8 | = tWRPRE − tCWL − 4 |
The old calculation reads 4 higher: CWL34/WRRD_dg52 → 8 versus 12. Historically, ASRock had the WTR error and MemTweakIt the WR error; version-dependent. Details: 3.7.
*Read CWL from the controller. Corrections: WR +1 with 2N, WTR −1 with a long write-signal ending. S ↔ dg, L ↔ sg; WTR is linked to WRRD, not RDWR.
In reverse: tWRRD = tCWL + 10 + tWTR*. With the same settings, WRRD +1 → WTR +1.
tRDRD_dg = tWRWR_dg = 8 - for DDR5/BL16, always leave these at 8 in the profile.
tWRWR_sg = 16 - the lowest effective value in my tests; lowering it further changes nothing. My own research.
ADDITIONAL TIMINGS: POWER AND REFRESH
tRDPDEN = tMRRPDEN = tCL + 8 + 1 = 45.
tWRPDEN = tWRAPDEN = tCWL + 8 + tWR + 1 = 34 + 8 + 48 + 1 = 91.
tACTPDEN = tPRPDEN = tREFPDEN = 2; tMRWPDEN = tMRD.
tXS = tRFC1; tXS_DLL = tDLLK for standard DDR5. Leave these parameters on Auto.
tCKE = 8. With PD = 0 (Power Down Disabled), tCKE/tXP and PD-entry delays do not affect this transition; they can stay on Auto.
tXP = 8 is only the cycle limit; PD = 1 also requires 7.5 ns: at 8200, at least 31. Sleep and self-refresh are separate modes.
OREF_RI = Auto; 0 removes the idle threshold for refresh, but does not disable refresh. Test any gain.
tREFI = interval, µs × MT/s / 2; round down. At 8200 and up to 85 °C: normal mode 3.9 µs → 15 990; FGR 1.95 µs → 7995. Above 85 °C, halve the intervals.
Steps: 16 383 → 32 767 → 65 535 → 131 071 → 262 143. At 8200: 4.00 → 7.99 → 15.98 → 31.97 → 63.94 µs. Field increment: 1; maximum 2¹⁸ − 1 (262 143). Use the maximum with active airflow or water cooling on the memory: stability depends strongly on temperature. Test with fully warmed memory.
RTL: ANTA777'S EMPIRICAL GUIDELINE
RTL ≈ MT/s / 800 + tCL + 19 = 8200 / 800 + 36 + 19 = 65.25. Training guideline, not ready-to-use values for the entire RTL group.