Glossary

12.1 Standards, platform, and controller

Basic names for the standard and platform. The English expansion is retained as the original name; the explanation column describes the term’s role in DDR5 tuning.

Table, PDF page 90
Term	English name	Explanation
DDR5	Fifth-Generation Double Data Rate Synchronous Dynamic Random-Access Memory	The fifth generation of synchronous dynamic memory with data transfers on both clock edges.
SDRAM	Synchronous Dynamic Random-Access Memory	Dynamic memory whose operation is synchronized to a clock signal.
DRAM	Dynamic Random-Access Memory	Volatile memory: data is stored as charge in cell capacitors. Periodic refresh is required to retain data.
JEDEC	Joint Electron Device Engineering Council	The organization that publishes DDR5 and SPD standards and timing requirements.
JESD79-5	JEDEC Standard 79-5: DDR5 SDRAM	The primary DDR5 device standard; its letter and version number identify the revision.
MT/s	Megatransfers per Second	Millions of transfers per second; the correct unit for effective DDR data rate.
MHz	Megahertz	Millions of clock cycles per second; for DDR, MT/s is approximately twice the physical fCK.
fCK	Clock Frequency	Physical frequency of the memory clock signal.
QCLK	Memory Controller Clock	Intel controller clock domain. For a confirmed Gear G mode: tQCLK = G x 2000 / MT/s, ns. Check utility readout units separately. See 5.7.
CPU	Central Processing Unit	Central processing unit; on LGA1700/LGA1851, it contains the memory controller.
Ring	Ring Interconnect	Ring interconnect linking cores, cache, and other CPU blocks on the LGA1700 platforms covered here; it is not the IMC itself.
IMC	Integrated Memory Controller	Controller integrated into the CPU: accepts requests, schedules DRAM commands, and services memory channels.
MC	Memory Controller	Intel memory-controller block; MC0/MC1 are its indices. The MC/C labels in ATC are explained in 5.7. MC is also part of the MC/VDD2 BIOS name.
Intel ME	Intel Management Engine	Intel platform-management subsystem with its own firmware; ME in a BIOS/ME label refers to it.
MRC	Memory Reference Code	Intel code inside the BIOS that initializes the IMC/PHY at startup and manages training.
FSP	Firmware Support Package	Intel package for platform initialization. Public FSP fields specify settings but do not expose the entire MRC algorithm.
PHY	Physical Layer	Physical interface layer: signal transmitters, receivers, delays, and calibrations.
BIOS	Basic Input/Output System	The familiar name for motherboard firmware and its settings menu; technically, a modern implementation is generally UEFI.
UEFI	Unified Extensible Firmware Interface	Modern firmware interface; also the environment from which MemTest86 runs.
POST	Power-On Self-Test	Initial self-test after power-on; a successful POST still does not prove stability.
POR	Plan of Record	An Intel-supported operating mode for a specific number of DIMMs, ranks, and data rate.
SKU	Stock Keeping Unit	Inventory identifier for a product. One SKU does not guarantee the same DRAM ICs across every batch; check the hardware revision separately.
Microcode	Processor Microcode	Low-level code controlling some CPU operations. Updates can be loaded by BIOS/UEFI or the operating system and can change processor behavior.
LGA	Land Grid Array	Type of CPU interface with contacts in the socket: LGA1700 and LGA1851.
PCH	Platform Controller Hub	Platform chipset that handles peripherals; it is not the IMC itself.
QVL	Qualified Vendors List	List of memory kits tested by the motherboard manufacturer in the stated configurations.
OC	Overclocking	Operation above the stock conditions of a specific component combination; XMP is also overclocking.

RTL/IOL ANALYSIS AND CALCULATION EXAMPLES — SECTION 5.7

DOCUMENTATION REVIEWED: Intel: Memory Controller, Microcode, FSP; JEDEC DDR5; Chapters 01-10, 14.

12.2 Modules, organization, and topology (continued)

PDF · 91Page 91

Module formats, support ICs, and DRAM construction. Rank organization, package placement, and topology are covered on the next page.

Table, PDF page 91
Term	English name	Explanation
DIMM	Dual In-line Memory Module	Full-size memory module with independent contacts on both sides of the PCB.
UDIMM	Unbuffered Dual In-line Memory Module	Ordinary unbuffered desktop module; commands reach DRAM without a register buffer.
SO-DIMM	Small Outline DIMM	Compact memory module for laptops and small systems; a standard DDR5 SO-DIMM has 262 contacts.
RDIMM	Registered DIMM	Module with a register that buffers commands, addresses, and the clock signal; used on compatible server platforms.
CUDIMM	Clocked Unbuffered Dual In-line Memory Module	UDIMM with a separate CKD driver that restores the clock signal.
CKD	Clock Driver	The IC on a CUDIMM that receives and reshapes CK; it does not train DQ/DQS lines.
RCD	Registering Clock Driver	RDIMM register buffer between the controller and DRAM for commands, addresses, and CK; it is not a DRAM device.
PMIC	Power Management Integrated Circuit	On-module controller generating VDD, VDDQ and VPP. Voltage range and control depend on the device model and configuration.
SPD	Serial Presence Detect	Module data set: organization, JEDEC profiles, XMP, and service information.
SPD Hub	Serial Presence Detect Hub	DDR5 IC that consolidates access to SPD, PMIC, and a temperature sensor.
EEPROM	Electrically Erasable Programmable Read-Only Memory	Rewritable nonvolatile memory in which SPD is stored.
XMP	Extreme Memory Profile	Enhanced Intel profile with frequency, timings, and voltages above the JEDEC baseline.
EXPO	Extended Profiles for Overclocking	AMD memory-overclocking profile for a compatible platform. Profile support and operation of a particular kit depend on the CPU, motherboard, and BIOS.
PCB	Printed Circuit Board	The printed circuit board of a module or motherboard; its routing affects the signal.
IC	Integrated Circuit	Integrated circuit. In a module description, it often means the complete packaged device; the term itself does not define the number of dies in the package.
Chip	Chip / Microchip	Colloquial name for a die or a complete DRAM device. When counting, clarify whether packages or dies are meant.
Package	IC Package	Structure around the die: substrate, protective encapsulation, and external contacts. Each separate component is counted when counting packages.
Substrate	Package Substrate	Small board inside a package: carries the die and connects it to the external contacts. Distinct from the module PCB.
FBGA	Fine-Pitch Ball Grid Array	Package with a fine-pitch array of solder balls underneath; the package designation does not specify die or rank count.
Die	Semiconductor Die	Piece of silicon on which the DRAM circuitry is fabricated: memory cells and control circuits.
Density	DRAM Die Density	Capacity of one die in Gbit; it determines many refresh requirements.
SDP / DDP	Single-Die Package / Dual-Die Package	One or two dies in one package. Die count alone does not determine rank count; organization and die selection matter.
MMR	Hynix MMR (Device Designation)	Hynix designation from the RAMGuide example: two 4 Gbit MFR dies (a DRAM revision) in a DDP package. This is not a separate rank type.
Low-loss	Low-Loss PCB Material	PCB material with low signal loss. This is a material property, not a guarantee of a particular memory data rate.
Back-drilling	Back Drilling	Removal of unused plated via stubs to reduce signal reflections.

DOCUMENTATION REVIEWED: JEDEC DDR5; AMD EXPO; module manufacturer documentation; Chapters 02, 14.

Package construction, rank organization, and PCB sides describe different properties. Next come DRAM width, channels, and slot routing.

Table, PDF page 92
Term	English name	Explanation
RDL	Redistribution Layer	Layer that redistributes die contact pads. In the DRAM packages discussed here, moving pads toward the edges facilitates wire bonding.
Monolithic DDR5	Monolithic DDR5 SDRAM	DDR5 devices with one DRAM die per package, without a 3DS stack. This describes the device, not the number of chips or ranks on the DIMM.
3DS / TSV	3D-Stacked DRAM / Through-Silicon Via	3DS is a stack of DRAM dies linked vertically by through-silicon vias (TSVs). Do not equate every DDP package with 3DS.
SS / DS	Single-Sided / Double-Sided	DRAM packages are soldered on one or both sides of the PCB. The number of sides does not determine rank count.
Rank	Memory Rank	Group of DRAM devices selected together by Chip Select; in DDR5, selection occurs by subchannel. Rank does not define the PCB side.
1R / 2R; R0 / R1	Single / Dual Rank; Rank 0 / Rank 1	One or two ranks on a module. R0 and R1 are rank numbers; 1R has R0, while 2R has R0 and R1.
x4 / x8 / x16	DRAM Device Data Width	DRAM data width: 4, 8, or 16 bits; by itself, it does not determine package or rank count.
1Rx4 / 1Rx8 / 2Rx8	Rank Count and Device Width	Notation for rank count and DRAM width: for example, 1Rx4 is one rank built from x4 devices.
Matched Kit	Factory-Matched Memory Kit	A kit tested by the manufacturer in precisely the stated composition.
Speed Bin	Speed Grade / Component Binning	Operating-class designation and the result of IC selection; an XMP bin is not the ultimate potential.
Non-binary DDR5	Non-Binary-Density DDR5	DDR5 with a die density that is not a power of two; for example, 24 Gbit with typical module capacities of 24 and 48 GB.
Channel	Memory Channel	Independent logical path between the IMC and memory.
Subchannel	Independent Memory Subchannel	One of two independent paths on a DDR5 DIMM: 32 data bits, or 40 bits with system ECC. These are not two CPU channels.
DPC / 1DPC / 2DPC	DIMMs Per Channel / One or Two DIMMs Per Channel	Number of modules actually installed per channel; a key measure of the current electrical load.
SPC / 1SPC / 2SPC	Slots Per Channel / One or Two Slots Per Channel	Number of slots physically routed per channel; this is a motherboard property, not the current DIMM installation.
true-1DPC	Community/Vendor Shorthand for True One-Slot-Per-Channel Topology	Common but terminologically imprecise name for a 1SPC motherboard; this manual uses SPC for routing.
2-DIMM / 4-DIMM	Two / Four DIMM Slots	Motherboard slot count; 2-DIMM models are generally optimized for memory overclocking.
Point-to-point	Point-to-point Memory Topology	A connection from the controller to the only DIMM slot on each channel. At the slot level, this routing corresponds to 1SPC.
Daisy Chain	Daisy-Chain Memory Topology	Daisy-chain routing of channel slots, generally preferred with one DIMM per channel.
T-topology	T-Topology Memory Routing	Branched routing with similar lengths to two slots, intended for 2SPC.
Gear	Memory Controller Gear Ratio	Ratio of MC frequency to the physical DRAM clock: Gear 2 = 1:2; Gear 4 = 1:4. Gear 2 is generally used with DDR5 on Raptor Lake.
OEM / reference	Original Equipment Manufacturer / Reference Module	In the catalog, desktop modules and reference entries; a supply category, not an IC type, rank count, or indication of ECC.
P/N / SKU	Part Number / Stock Keeping Unit	P/N is the manufacturer part number; SKU identifies a stock item. For a kit, keep the full code and suffix to distinguish capacity, profile and variant.
BOM	Bill of Materials	List of components making up a product. The manufacturer may change it between batches while retaining the product SKU.
DRAM revision	DRAM Die Revision	Die revision, not PCB revision or speed grade. S32M means Samsung DDR5, 32 Gbit, M-die.
Native JEDEC	Native JEDEC Speed Grade	Stock speed grade without XMP/EXPO. A component bin alone does not establish the SPD profile or rated operating mode of a finished module.

DOCUMENTATION REVIEWED: Micron: Monolithic RDIMM; Invensas: 3D Packaging; Chapters 02, 14.Micron: Monolithic RDIMM; Invensas: 3D Packaging; Chapters 02, 14.

12.3 Commands, buses, and signal paths

PDF · 93Page 93

DDR5 commands operate on banks, rows, and columns. Bus abbreviations show the physical path over which a command, address, or payload is transferred.

Table, PDF page 93
Term	English name	Explanation
Bank	Memory Bank	Independent array of rows and columns within DRAM.
Bank Group	Bank Group	Group of banks; transitions within one bank group and between different bank groups have different timings.
Row	Memory Row	Row of cells opened into the row buffer by an ACT command.
Column	Memory Column	Part of an open row accessed by read or write commands.
ACT	Activate	Opens the selected bank row before data access.
PRE	Precharge	Closes an open row and prepares the bank for the next activation.
PREab	Precharge All Banks	Closes open rows in every bank of the selected rank.
PREpb / PREsb	Precharge Per Bank / Same Bank	PREpb closes the selected bank; PREsb closes the bank with the same number in every bank group of the selected logical rank.
RD	Read Command	Command that reads data from an open row.
WR	Write Command	Command that writes data to an open row.
CAS	Column Address Strobe	Historical name for the column phase; appears in the names of CL and CAS-to-CAS timings.
RAS	Row Address Strobe	Historical name for the row phase; used in the names of ACT/PRE timings.
DQ	Data Input/Output	Bidirectional payload data lines between the IMC and DRAM.
DQS	Data Strobe	Data strobe used by the receiver to capture DQ bits.
CA	Command and Address	Command and address bus from the controller to the module.
CK	Clock	Primary differential memory clock signal.
CS / CS0 / CS1	Chip Select / Chip Select 0 / 1	Rank selection: CS0 corresponds to R0, and CS1 to R1. In DDR5, the select signals are independent for each subchannel.
CKE	Clock Enable (Legacy/Controller Term)	Historical and controller-side mode name; DDR5 has no separate CKE pin.
CMD / CTL	Command / Control	General labels for command and control signals.
MR / MRW / MRR	Mode Register / Mode Register Write / Read	DRAM mode register and its write/read commands. MRs configure modes and provide device-defined information; they are not SPD.
WCK	Write Clock	Separate high-speed LPDDR5 data clock; do not confuse it with CK on desktop DDR5.
BL16	Burst Length 16	A burst of 16 data transfers; the baseline burst length for DDR5.
BC8	Burst Chop 8	Shortened transfer of half a BL16 for a supported scenario.
Bus	Electrical Bus	A set of signal lines used to carry data, addresses, commands, or clock signals.
Turnaround	Bus Turnaround	Reversal of bus direction or change of bus target requiring a guard interval.
RMW	Read-Modify-Write	Read a block, modify part of it, and then write it back.

DOCUMENTATION REVIEWED: SK hynix DDR5 32Gb Rev.1.2: PRE/MR commands; Intel; Chapters 02-03.SK hynix DDR5 32Gb Rev.1.2: PRE/MR commands; Intel; Chapters 02-03.

12.4 Primary, secondary, and tertiary timings

PDF · 94Page 94

The letter t means time. Main BIOS timing fields are usually in CK cycles; maintenance fields may use other units. The same CK count at different MT/s represents a different time in nanoseconds.

Table, PDF page 94
Term	English name	Explanation
Timing	Memory Timing	Memory timing parameter: latency, duration, or interval between events.
tCK	Clock Period	Duration of one physical clock cycle: tCK, ns = 2000 / MT/s.
tCL	CAS Latency	Latency from the READ command until the first data appears.
tRCDRD	Row-to-Column Delay for Read	Interval from ACT to the subsequent READ command.
tRCDWR	Row-to-Column Delay for Write	Interval from ACT to the subsequent WRITE command.
tRP	Row Precharge Time	Time required to close a row before opening another row in that bank.
tRAS	Row Active Time	Minimum time for which a row remains open.
tRC	Row Cycle Time	Here, tRC = tRAS + tRP is a calculation. The actual ACT-to-ACT interval for the same bank can be longer because of the last READ/WRITE. See 3.3.
CR / 1N / 2N	Command Rate / One-N / Two-N	Command issue rate: every clock cycle or every other clock cycle.
tCWL	CAS Write Latency	Latency from WRITE to the start of data transfer.
tWR	Write Recovery Time	Minimum interval from the end of a write data burst to PRE for the same bank.
tRTP	Read-to-Precharge Time	Minimum interval from a READ command to PRE for the same bank.
tRRD_S / L	Row-to-Row Delay Short / Long	Interval between ACT commands: S for different bank groups, L for the same bank group.
tFAW	Four Activate Window	Minimum interval from the first to the fifth ACT in one rank; the window restarts with each new ACT.
tCCD_S / L	CAS-to-CAS Delay Short / Long	Interval between column commands: S for different bank groups, L for the same bank group.
tCCD_L_WR	Long CAS-to-CAS Write Delay	WR -> WR interval within one bank group when the second WRITE requires Read-Modify-Write.
tCCD_L_WR2	Long CAS-to-CAS Write Delay 2	Shortened WR -> WR interval within one bank group when the second WRITE does not require Read-Modify-Write.
tWTR_S / L	Write-to-Read Delay Short / Long	Interval from the end of a write data burst to READ: S for a different bank group, L for the same one.
tRDRD	Read-to-Read Delay	Family of tertiary transitions between two reads.
tWRWR	Write-to-Write Delay	Family of tertiary transitions between two writes.
tRDWR	Read-to-Write Delay	Bus turnaround from read to write.
tWRRD	Write-to-Read Delay	Bus turnaround from write to read.
S / L	Short / Long	Short and long timing variants. Their exact meaning depends on the timing family; they do not describe trace length.
sg / dg	Same Group / Different Group	Same or different bank group.
dr / dd	Different Rank / Different DIMM	Different rank or different module.

DOCUMENTATION REVIEWED: JEDEC DDR5, Intel and DRAM manufacturer documentation; Chapters 01-10, 14.

12.5 Refresh and maintenance intervals

PDF · 95Page 95

Refresh restores cell charge. Higher tREFI means less frequent refresh; lower tRFC means shorter refresh pauses. Both reduce overhead but increase sensitivity to temperature and the retention capability of the specific ICs.

Table, PDF page 95
Term	English name	Explanation
Refresh	DRAM Refresh	Periodic restoration of charge in memory cells.
Retention	Data Retention	A cell’s ability to retain data between refresh operations.
REFab	All-Bank Refresh	Refresh of all banks in the selected rank.
REFsb	Same-Bank Refresh	Refresh of the same-numbered bank in every bank group.
PBR	Per-Bank Refresh	Generic name for partial refresh. In Intel BIOS, Per Bank may refer to REFsb; it does not necessarily mean refreshing just one bank.
FGR	Fine Granularity Refresh	More frequent refresh with a shortened service cycle.
tREFI	Refresh Interval Time	Average interval between refreshes; increasing it reduces overhead and temperature margin.
tRFC	Refresh Cycle Time	Practical designation for the refresh-cycle duration actually applied by BIOS/MRC; converted to nanoseconds at the current data rate.
tRFC1 / tRFC2	Refresh Cycle Time 1 / 2	Requirements for normal REFab and REFab in 2x FGR mode, respectively; these are different standard modes, not two mandatory practical BIOS fields.
tRFCsb / tRFCpb	Same-Bank / Per-Bank Refresh Cycle Time	Platform-dependent names for a separate refresh path. In practice, tuned after tRFC.
tREFIx9	Maximum Refresh Interval	Refresh limit for one rank, in 1024 DCLK. Calculating 8 x tREFI / 1024 can exceed the field range. The result depends on the controller/MRC. Leave Auto.
Power Down	DRAM Power-Down State	Memory power-saving state while idle.
Self Refresh	Self-Refresh Mode	Mode in which DRAM performs refresh by itself.
tCKE	Clock-Enable Timing	Internal interval for entering and exiting Power Down.
tXP	Exit Power-Down Time	Delay from exiting Power Down until the next command.
tXS	Exit Self-Refresh Time	Delay when exiting Self Refresh.
tXS_DLL / tDLLK	Exit Self-Refresh DLL / DLL Locking Time	After Self Refresh, commands requiring the DLL must wait for it to be ready: tXS_DLL = tDLLK. This is a separate requirement from tXS.
tRDPDEN	Read-to-Power-Down Entry Delay	Interval from READ to entry into Power Down.
tWRPDEN	Write-to-Power-Down Entry Delay	Interval from WRITE to entry into Power Down.
tMRD / tMOD	Mode-Register Delay / Update Delay	Intervals between internal commands and application of a mode register.
tMRR	Mode Register Read Command Period	Minimum period between Mode Register Read (MRR) commands. Do not confuse the tMRR timing parameter with the MRR command itself.
ZQ Calibration	Impedance Calibration against ZQ	Calibration of DRAM output resistances against the ZQ reference.
tZQCSPeriod	ZQ Calibration Short Period	Interval at which short ZQ calibration is performed.
tZQOPER	ZQ Calibration Operation Time	Duration of a full ZQ-calibration operation.
RFM	Refresh Management	Mechanism for additional refresh under frequent activations; not a replacement for tRFC.
tRFM	Refresh Management Cycle Time	Minimum RFM-cycle duration; this is a timing parameter, not the RFM mechanism itself.
tRPab	All-Bank Precharge Time	Interval after PREab. Check the controller-specific scope of the field; do not automatically substitute the tRP setting.
tCA2CS	Command/Address-to-Chip-Select Delay	Internal interval between the CA path and CS selection.
Vendor fields	Controller/Vendor-Specific Timing Fields	Labels such as tSR, tOSCO, and tXPDLL are not expanded by guesswork and remain on Auto unless a specific task calls for them.

DOCUMENTATION REVIEWED: SK hynix DDR5 32Gb Rev.1.2: Mode Register Timing, Self Refresh; Intel; Chapter 03.SK hynix DDR5 32Gb Rev.1.2: Mode Register Timing, Self Refresh; Intel; Chapter 03.

12.6 Voltages and power domains

PDF · 96Page 96

Identical VDDQ letters in different menus do not mean the same physical rail. Record the name, measurement source, and platform together.

Table, PDF page 96
Term	English name	Explanation
Rail	Power Rail	A separate power rail with its own physical role.
DRAM VDD	DRAM Core Supply Voltage	Power for the array and internal peripheral circuits of DRAM devices.
DRAM VDDQ	DRAM I/O Supply Voltage	Power for the data interface on the module side.
CPU VDDQ TX	CPU Transmit I/O Supply Voltage	Power for the memory transmitter inside the CPU; not the same as DRAM VDDQ.
MC VDD / VDD2	Memory-Controller I/O Supply Voltage	Platform-specific names for the IMC interface rail, not two independent regulators.
SA / VCCSA	System Agent Supply Voltage	Power for the Intel System Agent; not a universal memory-frequency knob.
VPP	DRAM Wordline Pump Supply Voltage	Power for row activation, nominally about 1.8 V.
VDDIO	Input/Output Supply Voltage	Generic designation for the I/O power of a specific block.
VLDO	Low-Dropout-Regulator Output Voltage	Output of a local linear regulator, for example inside the SPD Hub.
LDO	Low-Dropout Regulator	Linear regulator with a low dropout voltage.
IVR	Integrated Voltage Regulator	Integrated CPU voltage regulator.
PMIC Sync All	Synchronize All PMICs	Applies the same control to the PMICs of all installed DIMMs.
Per-PMIC	Per-Power-Management-IC Control	Separate PMIC configuration for each module.
High DRAM Voltage	Extended DRAM-Voltage Range Mode	Extended VDD/VDDQ range on compatible PMICs; does not set voltage.
VOUT	Voltage Output	Regulator output voltage; in monitoring, its telemetry reading.
VID	Voltage Identification	Requested voltage, which does not have to match VOUT under load.
SVID	Serial Voltage Identification	Intel digital interface for power control and telemetry.
LLC	Load-Line Calibration	Compensation for voltage droop under current load; aggressive LLC may cause overshoot.
PLL	Phase-Locked Loop	Loop that synchronizes and recovers frequency and phase.
DLL	Delay-Locked Loop	Loop that aligns delays without synthesizing a new frequency.
TDDB	Time-Dependent Dielectric Breakdown	Time-dependent dielectric breakdown: insulation damage from prolonged electrical stress.
ppm	Parts Per Million	One millionth; 1 ppm = 1 in 1,000,000. In the TI chart, this is the calculated failure fraction.
TCASE	DRAM Package Case Temperature	DRAM package case temperature at the specified measurement point. The SPD Hub sensor reading is not a direct TCASE measurement.
VRM	Voltage Regulator Module	Power circuitry for the CPU or another rail. Phase count and power-stage ratings alone do not determine memory overclocking.
PWM	Pulse-Width Modulation	A PWM controller regulates the power converter by controlling the switching pulses sent to its phases.
SPS	Smart Power Stage	Integrated power stage with a driver and protection functions. Its current rating is not the current capability of the whole board.
PMIC5120	JEDEC PMIC5120	JEDEC PMIC class for client DDR5; Renesas RRG5332 is one example. The class does not identify a silicon revision.

DOCUMENTATION REVIEWED: JEDEC DDR5, Intel and DRAM manufacturer documentation; Chapters 01-10, 14.

12.7 Termination and signal integrity

PDF · 97Page 97

ODT, driver resistance, and Vref define the electrical receive window. Their goal is not the lowest number, but a clean signal with margin in every bus state.

Table, PDF page 97
Term	English name	Explanation
ODT	On-Die Termination	Line termination using resistors integrated into the die. Active termination depends on transfer direction and rank state.
RTT	Termination Resistance	Generic designation for ODT resistance; not a separate technology.
RTT_NOM	Nominal Termination Resistance	Nominal termination for the selected DRAM state.
RTT_WR	Write Termination Resistance	DRAM termination during writes.
RTT_PARK	Park Termination Resistance	Termination of an inactive, parked rank.
RON	Driver On-Resistance	Output resistance of the active transmitter.
PU / PD	Pull-Up / Pull-Down	Upper and lower parts of the driver or termination.
Vref	Reference Voltage	Reference level for distinguishing a logical zero from one.
VrefDQ	Data Reference Voltage	Reference level of the DQ data path.
VrefCA	Command/Address Reference Voltage	Reference level of the CA command/address path.
VrefCS	Chip-Select Reference Voltage	Reference level for receiving CS; distinct from VrefCA and VrefDQ. Adjustable only when the platform provides the corresponding field.
Drive Strength	Transmitter Drive Strength	Output-stage strength; the maximum value is not necessarily optimal.
Power Training	DDR I/O Power Training	MRC stage that selects ODT, driver strength, and related buffers to reduce DDR I/O power while preserving operating margin.
Slew Rate	Signal Slew Rate	Rate of a signal edge’s rise and fall.
EQ	Equalization	Compensation for frequency-dependent channel loss and distortion.
CTLE	Continuous-Time Linear Equalizer	Linear receiver equalizer.
DFE	Decision-Feedback Equalization	Distortion correction based on previously received symbols.
DCC	Duty-Cycle Correction	Duty-cycle correction for CK, DQS, DQ and other PHY signals.
DCA	Duty-Cycle Adjuster / Adjustment	DRAM signal duty-cycle tuning.
PVT	Process, Voltage, Temperature	Process, voltage, and temperature variation accounted for by calibrations.
Eye	Signal Eye	Permissible time and voltage ranges for correct signal reception.
Margin	Signal Margin	Margin to the error boundary; not a guarantee of operating-system stability.
Crosstalk	Signal Crosstalk	Electromagnetic coupling between adjacent lines.
Tap	Delay Tap	Discrete increment of a programmable delay line.
Bypass	Bypass Mode	Circuit/path bypass; VccDLL Bypass reroutes power while the DLL remains active.

DOCUMENTATION REVIEWED: JEDEC DDR5, Intel and DRAM manufacturer documentation; Chapters 01-10, 14.

12.8 Training, booting, and recovery

PDF · 98Page 98

Training selects delays, Vref, and compensation for the current startup. One successful POST may not be repeatable, so both cold and warm boots must be checked.

Table, PDF page 98
Term	English name	Explanation
Memory Training	Memory Interface Training	Selection of delays, Vref, ODT, and memory-interface compensation.
Auto	Automatic Firmware-Controlled Value	A BIOS/MRC decision; does not necessarily mean a standard or minimum value.
Trained Value	Value Determined by Training	Actual value found by the current training cycle.
Full Training	Full Memory Training	The complete BIOS/MRC cycle configured for the current system; its stages depend on the platform and settings.
Full Retrain	Full Memory Retraining	Another full training cycle after conditions change.
Cold Training	Training after a Cold Start	Training after power removal; not every cold start guarantees a complete MRC cycle.
1D / 2D	One-/Two-Dimensional Training	A search across one or two tuning parameters.
RDTC2D	Read Timing Centering 2D	Switch for a training stage in Intel FSP and corresponding BIOS implementations. Not a numerical timing; its exact use depends on the firmware.
Per-Bit	Per-Bit Training	Individual calibration of each DQ bit.
MPR	Multi-Purpose Register	In DDR4, a pattern register; DDR5 training patterns use MR settings.
WL	Write Leveling	Alignment of write DQS relative to CK.
RTL	Round-Trip Latency	Intel Alder Lake / Raptor Lake field: READ to first data at the MC, per rank, in QCLK. Utility scaling and conversion to ns require verification. See 5.7.
RTLA / RTLB	Round-Trip Latency A / B	A/B-side designations in the empirical formula; they do not automatically correspond to every MC/C row in ATC. See 5.7.
IOL	I/O Latency	Separate I/O delay in the BIOS of some DDR4 platforms. On DDR5, the parameters and access to them are arranged differently. See 5.7.
RTL Init	Round Trip Latency Initial Value	Initial RTL search setting during training; not a promise of the final RTL.
RTL Max	Round Trip Latency Maximum	Upper bound of the RTL search during training in ASUS BIOS; does not guarantee that final result.
RTL Offset	Round Trip Latency Offset	RTL offset with separate sign and magnitude in ASUS BIOS; behavior depends on the implementation. Not a universal rule to subtract 1–2.
TAT	Turn-Around Timing	Transition intervals between bus directions and targets.
RMT	Rank Margin Tool	Tool for evaluating a rank’s timing and voltage margin.
Cold Boot	Cold Boot / Cold Start	Startup after shutdown; the state of standby power must be specified.
AC Cold Start	Cold Start after AC-Power Removal	Startup after complete removal of external and standby power.
Warm Restart	Warm Boot / Warm Restart	Restart without complete power removal.
S5	ACPI S5 Soft-Off State	Software-initiated operating-system shutdown that may preserve standby power.
MRC Fast Boot	Memory Reference Code Fast Boot	Shortened memory reinitialization path.
BIOS Fast Boot	Firmware Fast Boot	Shortens overall POST; not the same as MRC Fast Boot.
Windows Fast Startup	Operating-System Fast Startup	Hybrid Windows shutdown; not a cold boot.
No-POST	Failure to Complete POST	The system did not complete hardware initialization.
Recovery	Firmware Recovery Procedure	Return to bootable settings after a failed POST.
Clear CMOS	Clear CMOS Settings (CMOS: Complementary Metal-Oxide-Semiconductor)	Reset of saved BIOS settings; CMOS is a historical name here.
DIMM Fit	ASUS DIMM Fit	Automatic search for parameters around an already bootable baseline.
DIMM Fit Pro	ASUS DIMM Fit Pro	Extended ASUS process for selecting and testing memory parameters.
Training Consistency	Memory-Training Consistency	Feature for improving training repeatability, not a stress test.
Memory Preset	Firmware Memory Preset	Manufacturer-prepared set of baseline memory settings.

RTL/IOL ANALYSIS AND CALCULATION EXAMPLES — SECTION 5.7

DOCUMENTATION REVIEWED: Intel FSP Raptor Lake-S: RDTC2D; ASUS BIOS manuals; Chapter 05.

12.9 Profiles, errors, and stability

PDF · 99Page 99

Stability always refers to stated conditions. POST, a benchmark pass, one screenshot, and daily reliability are different levels of evidence.

Table, PDF page 99
Term	English name	Explanation
Baseline	Baseline Configuration	Recorded starting configuration for a controlled comparison.
Profile	Saved Configuration Profile	Saved set of settings and conditions; by itself, does not prove stability.
Daily	Daily-Validated Profile	Daily profile with validated thermal and electrical margin.
Benchmark profile	Benchmark-Stable Profile	Settings validated only by the stated benchmark.
Screenshot profile	Screenshot-Only Profile	Profile for capturing settings without full validation.
Safe JEDEC	Safe JEDEC Baseline	Backup stock profile for system recovery.
Validation	Configuration Validation	Checking against specified conditions. In CPU-Z/HWBOT, also registration of settings or a result; it does not by itself prove stability.
Stability	Operational Stability	Absence of errors under the listed conditions and scenarios.
Pass	Successful Test Pass	Completed pass without logged errors.
Fail / Error	Test Failure / Detected Error	Test error or failure; the result requires diagnosis and does not count as a pass.
Coverage	Test Coverage Percentage	An internal program metric, not a probability of overall stability.
Cycle	Test Cycle	One complete set of algorithms in a particular test.
A/B Test	Controlled A/B Comparison	Comparison of two variants with one variable changed.
Sweet Spot	Optimal Operating Window	Best balance of results, temperature, voltage, and repeatability.
Hot Stability	Stability at Thermal Equilibrium	Stability after memory and the system reach their thermal plateau.
Thermal Margin	Temperature Margin	Margin to the temperature at which errors appear.
Pre-OS	Pre-Operating-System Environment	Environment before Windows loads, such as UEFI MemTest86.
ECC	Error-Correcting Code	Code for detecting and correcting data errors.
On-die ECC	On-Die Error-Correcting Code	Internal error correction within a DRAM die; does not protect the entire data-transfer path.
ECS	Error Check and Scrub	Checks and corrects stored data using on-die ECC, with the specified counters. Reading them requires platform support; this is not a system ECC report.
Side-band ECC	Side-Band Error-Correcting Code	System-level correction using additional ECC bits; requires a compatible CPU/IMC, motherboard, and ECC DIMM.
Corrected ECC errors	Corrected ECC Error Events	Corrected and logged ECC errors; increases must not be ignored.
ECC injection	Error-Correcting Code Error Injection	Deliberate introduction of an error to verify ECC operation.
WHEA	Windows Hardware Error Architecture	Windows subsystem that logs hardware errors.
DMA	Direct Memory Access	Direct device access to memory without normal CPU data handling.
NUMA	Non-Uniform Memory Access	Architecture in which the cost of accessing different memory regions varies.
CRC	Cyclic Redundancy Check	Checksum used to detect data corruption.
Row disturbance / Row Hammer	Row-Disturbance Bit Flips / Row Hammer	Data errors in victim rows caused by repeated activations of aggressor rows. A particular scenario can involve multiple rows.
PPR	Post-Package Repair	Row repair: Soft PPR is temporary; Hard PPR survives power loss.

DOCUMENTATION REVIEWED: SK hynix DDR5 32Gb Rev.1.2: ECS; test documentation; Chapters 07, 10.SK hynix DDR5 32Gb Rev.1.2: ECS; test documentation; Chapters 07, 10.

12.10 Tools, workloads, and metrics

PDF · 100Page 100

A stress test searches for errors; a benchmark measures a result.

Table, PDF page 100
Term	English name	Explanation
Stress Test	Stress Test	Workload used to find errors, not to achieve a record result.
Component Stress	Component-Specific Stress Test	Algorithm that deliberately loads the CPU, IMC, or RAM.
y-cruncher	y-cruncher Component Stress Tester	Set of computational workloads for the CPU, IMC, and memory.
SVT	Small In-Cache VT3	Small in-cache variant of the VT3 family: primarily tests CPU/cache without a large RAM working set.
VT3	Vector-Scalable Transform, Version 3	Direct replacement for the obsolete VST: heavy floating-point workload with a large CPU + IMC + RAM working set.
FFT	Fast Fourier Transform	Fast Fourier transform; intensive floating-point and memory operation.
NTT	Number-Theoretic Transform	Integer number-theoretic transform.
AVX	Advanced Vector Extensions	Set of wide vector instructions for the CPU.
FPU	Floating-Point Unit	Compute unit for floating-point operations.
TM5	TestMem5	Windows memory-testing engine with pluggable configs.
Karhu	Karhu RAM Test	Test of an allocated amount of RAM in Windows; progress is reported as coverage.
MemTest86	PassMark MemTest86	UEFI memory test run before the operating system starts.
RAM Test Pro	PCSTONKS RAM Test Pro	Windows utility with configurable memory tests, error logging and WHEA monitoring.
OCCT	Historically: OverClock Checking Tool	Suite of platform stress tests and benchmarks; the product’s current name is OCCT.
AIDA64	AIDA64 Cache & Memory Benchmark	Measures Read, Write, Copy, and synthetic latency.
MLC	Memory Latency Checker	Intel tool for measuring latency and bandwidth.
CPU-Z	CPU-Z	Shows the CPU, motherboard, active memory parameters, and SPD.
ATC	ASRock Timing Configurator	Utility for viewing memory timings and RTL; the set of fields depends on the platform and version. See 5.7.
HWiNFO	HWiNFO	Tool for monitoring sensors, minimums, and maximums.
Benchmark	Performance Benchmark	Performance measurement; not a stability test.
Latency	Access Latency	Time spent waiting for access or a response, generally in nanoseconds.
Bandwidth	Memory Bandwidth	Amount of data transferred per unit of time.
Throughput	Sustained Throughput	Actual stream performance including overhead.
GB/s / ns	Gigabytes per Second / Nanoseconds	Units of bandwidth and latency.
Median / P1 / P99	Median / First / Ninety-Ninth Percentile	Central result and distribution tails; the metric’s direction must be stated.
FPS / 1% Low	Frames per Second / Slowest-One-Percent Frame Metric	Average frame rate and a measure of rare slow frames; the calculation method must be recorded.
Frametime	Frame Time / Frame Interval	Interval between consecutive frames or Present events; the precise meaning depends on the selected metric.
CPU-/GPU-limit	CPU-/GPU-Limited Workload	CPU or GPU limitation that changes how visible the RAM effect is.
Throttling	Thermal/Power Throttling	Automatic frequency reduction due to temperature, current, or a power limit.
Gbit / GB	Gigabit / Gigabyte	Die density in bits and module capacity in bytes are different quantities; 8 bits = 1 byte. Do not confuse Gbit, GB, and binary GiB.

DOCUMENTATION REVIEWED: JEDEC DDR5, Intel and DRAM manufacturer documentation; Chapters 01-10, 14.

12.11 ADVANCED TRAINING ALGORITHMS

PDF · 101Page 101

Terms used in the advanced analysis of memory training.

Training Algorithms terms, PDF page 101
Term	English name	Explanation
RxVref	Receiver Reference Voltage	The CPU receiver's decision threshold during reads. It is adjusted separately from DRAM VrefDQ, which is used during writes.
DQS gating	DQS Receive Gating	Controls the DQS receive window so that the receiver opens for the expected start of a read transfer.
Deskew	Timing Deskew	Compensation for timing differences between signal lines. Per-bit deskew adjusts the timing of individual DQ bits separately.
FIFO	First In, First Out	A buffer that releases data in the order received. Receive-FIFO delays help align returning data with the memory controller.
PI	Phase Interpolator	A phase interpolator positions a signal edge between available clock phases.
LVR	Linear Voltage Regulator	A linear voltage regulator. In the Intel architecture discussed here, these regulators supply internal memory-PHY circuits.
LFSR	Linear Feedback Shift Register	A shift register with linear feedback that generates pseudorandom bit sequences used in training patterns.
Swizzle	DQ/DQS Swizzle	The mapping of logical DQ/DQS signals to physical routing, accounting for permitted signal permutations.
Address aliasing	Address Aliasing	Different logical addresses refer to the same physical memory location. An incorrectly described DRAM organization can cause this.
BDAT	BIOS Data ACPI Table	An ACPI table for diagnostic data, including RMT results. Its generation is enabled separately and does not guarantee a visible BIOS report.