Memory training and the tuning process

Tuning starts not with someone else's timings, but with a repeatable baseline. First prove that the system works correctly on clean JEDEC/Auto, then establish a separate XMP baseline. Old manual voltages, trained values, or hidden profile settings must not be carried between these modes.

TWO BASELINES FOR TWO DIFFERENT TASKS

RECORD FOR EACH SESSION

WHY THE ORDER STARTS WITH CAPACITY, NOT MT/s

Capacity determines the available module organization and electrical load before an impressive frequency is chosen. A 2 x 48 GB kit usually requires a different strategy from 2 x 24 GB, even with the same IC manufacturer: rank count, training, ODT, temperature, and the controller's realistic ceiling all change. Gear (the controller divider) and Command Rate (the command interval) are selected after the target load. Only then does it make sense to find useful SA, TX, MC, VDD, and VDDQ ranges. This keeps every failure explainable and prevents excess voltage from masking an incorrectly chosen baseline.

Memory Reference Code (MRC) is part of Intel firmware that selects working delays, reference-voltage levels, termination, and signal compensation during startup. The result is a set of parameters with which the system can continue booting. This is not a stability test under load and not an automatic search for the best timings.

ASUS SERVICE SETTINGS

The table combines the public ASUS Z790 BIOS manual with the actual Apex Encore BIOS 2202 menu. In Auto, MRC/ASUS selects the state of each function. The final column is my practical A/B scheme for Z790 Apex Encore / BIOS 2202 / 2 x 24 GB DDR5-8200. For another motherboard, CPU, kit, or BIOS, start with Auto.

The Z890 menu exposes more PHY/MRC stages. The starting scheme below uses the ASUS manual and my recommendations. I leave most stages on Auto; choices for manual timing adjustments are shown in the table and Chapter 06.

WHAT RTL IS ON DDR5

RTL is Round-Trip Latency, the delay of the full read path. In Intel documentation for Alder Lake / Raptor Lake, it is the interval from the READ command until the first data returns to the memory controller, expressed in QCLK cycles. Training selects receiver parameters while accounting for the CPU, motherboard, modules, and settings. RTL is not CAS or AIDA64 latency.

IOL is I/O Latency. On DDR4, it is a separate I/O delay setting. On DDR5, receiver parameters and their availability depend on the platform and BIOS; the old RTL/IOL pairing cannot be carried over.

WHAT TO USE AS YOUR REFERENCE

The main reference is repeatability on your own stable profile. Under identical conditions, a higher RTL, a new spread between corresponding entries, and boot-to-boot jumps are warning signs, especially when accompanied by repeated POST attempts, test errors, or performance loss.

1. Create comparable conditions. Save frequency, Gear, CAS, voltages, BIOS, and ME in a profile. Compare several full training cycles using the same boot method: a restart with MRC Fast Boot may reuse a saved result.

2. Record the result of each boot. Compare the same active controller, subchannel, and rank positions. Note boot time and Karhu / y-cruncher errors; measure performance the same way each time.

3. Change one parameter. If the result varies, test a lower frequency or looser CAS, then voltages separately. Repeat training and tests to verify reproducibility.

WHY THE RESULT MAY CHANGE

MANUALLY LOWERING RTL IN BIOS

For EVGA DARK, the community reported RTL reductions of 1-2, supposedly by lowering CAS: the RTL block would then train according to the selected CAS. ASUS Z790 documents RTL Init / Max, a signed Offset, and rank fields. I tested these blocks and concluded that they should remain on Auto. The motherboard should perform the training itself. If the result is unusable, diagnose it (see the glossary). For Z690 Tachyon, there are reports that manual entry does not work and recommendations to enable RTL training; no conclusion has been established for Z790.

anta777 EMPIRICAL FORMULA

anta777 has an empirical formula for estimating RTL. Effective DDR5 data rate in MT/s and CAS in cycles are entered into it, and the result is used as an approximate reference.

A technically exact universal relationship has not been confirmed. Do not force every utility entry to 65 / 66. The rule that "RTLA rounds down and RTLB rounds up" cannot be considered universal: when the fractional part is below 0.50, the lower integer RTLB value also occurs. In this case, this is an observation from readings, not proof of the BIOS rounding algorithm.

XTREEM CASE STUDY: 8200 AND 8400 MT/s

ASUS ROG Maximus Z790 Apex Encore, TEAMGROUP T-Force XTREEM 2 x 24 GB, Gear 2. We compare ATC readings for three profiles: 8200 @ tCL38, 8200 @ tCL36, and 8400 @ tCL38.

How to read an entry. MC0 / MC1 are controller blocks; C0 / C1 are the two 32-bit DDR5 paths within each block. A1/A2 and B1/B2 label groups of positions in ATC. Apex Encore physically has two slots.

What 70/25 means. The slash separates two RTL readings in one entry. 70 applies to the occupied position; 25 in the second position matches Intel's reset value of 0x19. For this 1R kit, 25 is consistent with an unused position.

Relationship to the formula. At 8200, C1 matches the lower integer from the anta777 estimate: 67.25 -> 67 at tCL38, 65.25 -> 65 at tCL36. At 8400 @ tCL38, the estimate is 67.5, but C1 stays at 67; the entire RTL block matches 8200 @ tCL38. C0 is 5 / 6 above C1. The formula does not directly describe the whole block; the screenshots do not explain the offset or rounding algorithm.

The basic validation remains the same: several full training cycles, comparison with a stable profile, tests, and identical performance measurements. My 8200 @ tCL36 profile also showed RTL 64/65. One screenshot proves neither normal behavior nor an error. Under the confirmed conversion conditions in Section 5.7 (p. 47), at 8200 MT/s and Gear 2 one QCLK is approximately 0.488 ns: a difference of 5-6 conditionally corresponds to 2.44-2.93 ns. The ATC 4.1.7 scaling on this system has not been confirmed. This is a calculated read interval, not a measurement of overall latency or stability margin.

I treat Apex and other prominent 2-DIMM motherboards as the benchmark for correct, fast RTL training when comparing them with other boards, especially 4-DIMM models.

WHAT TO ACCOUNT FOR ON Z890

On Z890 / Core Ultra 200S, use documentation and a utility intended for that platform: field names, units, and training procedures may differ. ASUS BIOS includes Training Consistency, which may improve training repeatability but does not replace testing. Z790 numbers and offsets, including the anta777 estimate, cannot automatically be treated as targets for Z890.

The public menu separates Read DQ/DQS ODT more precisely, exposes more PHY calibrations, and adds Training Consistency and the DIMM Fit family. The absence of an old name does not prove removal of the algorithm: it may have been merged, renamed, or hidden within the MRC.

CUDIMM: CKD RESTORES THE CLOCK BUT DOES NOT TRAIN THE DATA PATH

DIMM FIT: AUTOMATIC SEARCH FROM A GIVEN STARTING POINT

WHAT REMAINS VALID AFTER AUTOMATIC TUNING

DIMM Fit optimizes parameters only relative to the current starting point. After changing frequency, Gear, voltage, kit, or CKD mode, repeat training and tests for the saved Store. CKD improves clock-signal quality on CUDIMM, but does not prevent read/write data errors caused by unsuitable Vref/ODT settings or memory temperature. High Z890 frequencies cannot be explained by one CKD entry or attributed to Gear 4.

FOR ADVANCED USERS. GENERALLY NEEDED FOR EXTREME OVERCLOCKING. FOR ORDINARY TUNING, ALWAYS LEAVE THESE SETTINGS ON AUTO.

ODT is line termination integrated into the die; RTT is its selected effective resistance; RON is the output resistance of the active transmitter. A lower number means stronger termination or output drive, but not automatically a better signal: excessive strength also creates ringing, overshoot, and crosstalk.

WHAT THE RESISTANCES ACTUALLY CONTROL

PRACTICAL POINTS FOR Z790 / Z890 APEX, STARTING AT 8400 MT/S

All resistances are in Ω. Historical examples do not replace Auto or validation on your own system.

Save a working step after each completed stage. Then a failed timing or voltage change will not force you to rebuild the profile: you can quickly return to the last repeatable point and test the next hypothesis separately.

Changing frequency or Gear requires retesting voltage ranges and training repeatability. When changing the CPU, kit, capacity, occupied slots, BIOS version, or UDIMM/CUDIMM type, it is safer to start from the baseline profile.

PROFILE LADDER: ROLLBACK SHOULD TAKE SECONDS

RECOVERY ORDER AFTER A FAILED POST