ADVANCED ANALYSIS OF TRAINING ALGORITHMS

Early Command Training — ECT

What it does. Finds an initial working alignment of the command and control signals relative to CLK for the subsequent stages.

Practical choice. AUTO. Test ENABLED separately if full training fails with a new profile.

Key detail. The older implementation handles LPDDR. The specific CA/CS passes for DDR5 on Z790/Z890 have not been publicly confirmed.

Command Voltage Centering — CMDVC

What it does. Centers command Vref, the threshold for detecting commands.

Practical choice. AUTO; test ENABLED with automatic command Vref and inconsistent training results. DISABLED if centering repeatedly produces poor results or when manually tuning the same Vref.

Key detail. DDR5 has VrefCA and VrefCS; the exact scope of this BIOS stage has not been disclosed.

Early Command Voltage Centering

What it does. The name suggests early command Vref tuning; the exact implementation and how it differs from CMDVC have not been established.

Practical choice. AUTO.

Key detail. The option is listed for Z790; it is not listed in the Z890 manual reviewed.

Late Command Training — LCT

What it does. Performs late centering of CMD/CTL relative to CLK; the older code uses complex command patterns.

Practical choice. AUTO; ENABLED when selecting training stages manually while leaving command delays on automatic. Test DISABLED if this late adjustment reproducibly makes the result worse.

Key detail. Early and Late complement each other.

CMD CTL CLK Slew Rate — CMDSR

What it does. Tunes Slew Rate (the rate of voltage change at signal edges) for the command, control, and clock lines based on the operating window.

Practical choice. AUTO with automatic electrical settings. Test DISABLED when manually tuning the corresponding Slew Rate settings, or if the automatic stage reproducibly makes the result worse.

CMD/CTL DS & E 2D — CMDDSEQ

What it does. Jointly tunes command driver strength and transmitter equalization: Drive Strength × Tx Equalization.

Practical choice. AUTO; test DISABLED when manually tuning these parameters if the stage prevents the combination from being retained.

Key detail. Z890 lists separate CMD/CTL Drive Strength — CMDDS and CMD/CTL Tx Equalization — CMDTXEQ controls.

CMD/CTL Drive Strength Up/Dn 2D — CMDDRUD

What it does. Separately tunes the pull-up and pull-down strengths of the command drivers: pull-up × pull-down.

Practical choice. AUTO; test DISABLED when manually tuning the command Up/Dn settings specifically, or when automatic training repeatedly produces a poor result.

Key detail. The corresponding option/flag was not found in the Z890 manual reviewed or in the Arrow Lake-S interface.

SenseAmp Offset Training — SOT

What it does. Calibrates the inherent electrical offset of the CPU’s DQ/DQS input receivers, compensating for variation in their detection thresholds.

Practical choice. AUTO. At the overclocking limit, if results differ between training runs, test DISABLED separately; keep it only if boot behavior and test results improve repeatably.

Early ReadMPR Timing Centering 2D — ERDMPRTC2D

What it does. Searches for an initial read region across DQ/DQS timing and RxVref. The older algorithm centers timing at different RxVref values using a known pattern, without requiring functional writes to normal memory.

Practical choice. AUTO. Test ENABLED separately if full training fails or produces inconsistent results.

Key detail. Early Read Time Centering 2D uses normal test traffic.

Read MPR Training — RDMPRT

What it does. Aligns DQ reads relative to DQS using a known pattern: finds the timing boundaries of the operating window and selects a position within it.

Practical choice. AUTO; ENABLED when manually enabling the basic training stages.

Receive Enable Training — RCVET

What it does. Locates the arrival of the DQS preamble and sets when the receive window opens — DQS gating.

Practical choice. AUTO; ENABLED when manually enabling the basic training stages. Disable it only to diagnose a specific, reproducible failure.

Receive Enable Centering 1D — RCVENC1D

What it does. Further centers Receive Enable along the timing axis.

Practical choice. On Z790 Apex / Encore — AUTO.

Key detail. The older Coffee Lake description includes LPDDR Only. The option/flag was not found in the Z890 manual or the Arrow Lake-S IoT FSP reviewed.

Jedec Write Leveling — JWRL

What it does. Aligns DQS relative to CK on the memory side, compensating for the difference in their delays. The controller uses feedback from DRAM to position the write strobe.

Practical choice. AUTO; ENABLED when controlling the basic training stages manually.

Key detail. DDR5 also provides compensation for mismatched internal DQ/DQS paths.

Early Write Time Centering 2D — EWRTC2D

What it does. Performs a preliminary search for a working write region: centers DQ/DQS timing at several DRAM VrefDQ values and selects a suitable starting point.

Practical choice. AUTO. Test ENABLED or DISABLED separately when troubleshooting full training.

Key detail. In the older MRC code reviewed, this stage is allowed only for DDR4. The field in current FSP does not disclose the conditions under which it runs for DDR5. The Z790 manual uses Timing instead of Time in the name.

Write Timing Centering 1D — WRTC1D

What it does. Finds the write window and centers DQ timing relative to DQS at the current VrefDQ.

Practical choice. AUTO where available; in menus with only ENABLED / DISABLED, start with ENABLED. Keep the selected basic centering mode when enabling the late 2D pass.

Key detail. E21287 and E22758 for Z790 offer only ENABLED / DISABLED; E25061 for Z890 also offers AUTO.

Write Voltage Centering 1D — WRVC1D

What it does. Centers VrefDQ, the internal threshold for detecting write data in DRAM, at the current DQ/DQS timing position.

Practical choice. AUTO; ENABLED when manually enabling the basic training stages. Test DISABLED if centering repeatedly produces poor results or when manually tuning this same DRAM VrefDQ.

Key detail. Even with manual VDD/VDDQ settings, the DRAM VrefDQ threshold is tuned separately.

Write Timing Centering 2D — WRTC2D

What it does. Refines the DQ/DQS timing position, accounting for changes in the operating window at different VrefDQ values.

Practical choice. AUTO. At a borderline overclock, test ENABLED separately if stability varies after repeated training. Keep DISABLED only if it produces a repeatable improvement over the initial mode.

Key detail. The reference stage may include per-bit deskew: individual compensation for timing variation between bits.

Write Voltage Centering 2D — WRVC2D

What it does. Measures the voltage boundaries of the operating window at several DQ/DQS timing offsets and uses the combined results to refine VrefDQ.

Practical choice. AUTO. Test ENABLED separately if stability after training is borderline. DISABLED if centering is demonstrably poor or when manually tuning the same VrefDQ.

Early Read Time Centering 2D — ERDTC2D

What it does. Performs a preliminary search for a read operating point across DQ/DQS timing and RxVref; the reference code checks it using normal test traffic.

Practical choice. AUTO. Compare ENABLED / DISABLED separately when troubleshooting full training.

Key detail. In the older MRC code reviewed, ERDTC2D is restricted to DDR4; the conditions used by the current DDR5 implementation have not been disclosed. The Z790 manual spells the name Early Read Timing Centering 2D.

Read Timing Centering 1D — RDTC1D

What it does. Finds the timing boundaries for receiving data and centers the DQ sampling time relative to DQS on the controller side at the current RxVref.

Practical choice. AUTO; ENABLED when controlling the basic training stages manually. When enabling RDTC2D, keep the selected RDTC1D mode: basic and subsequent centering may run one after the other.

Read Timing Centering with JR

What it does. A separate read timing centering variant in the Z790 menu. How it differs from RDTC1D has not been established.

Practical choice. AUTO.

Key detail. The meaning of JR has not been confirmed. This option is not listed in the Z890 manual reviewed.

Read Voltage Centering 1D — RDVC1D

What it does. Centers RxVref, the memory controller’s data detection threshold, at the current DQ/DQS timing position.

Practical choice. AUTO; ENABLED with automatic RxVref when controlling the basic training stages manually. Test DISABLED for poor results or manual RxVref tuning, provided a comparison confirms that this pass is interfering.

Key detail. Even with manual VDDQ or SA settings, the RxVref threshold is tuned separately.

Read Timing Centering 2D — RDTC2D

What it does. Refines the data sampling time based on the shape of the operating window at different RxVref values.

Practical choice. AUTO. At a borderline overclock, test ENABLED separately if stability varies after repeated training. Keep DISABLED only if it produces a repeatable improvement.

Key detail. The reference stage may perform per-bit deskew: individual compensation for timing variation between bits.

Read Voltage Centering 2D — RDVC2D

What it does. Refines RxVref using the voltage boundaries of the operating window, measured at several DQ/DQS timing offsets.

Practical choice. AUTO. Test ENABLED separately with inconsistent training results and automatic RxVref. DISABLED if centering is confirmed to be poor or when manually tuning the same threshold.

Dimm ODT Training — DIMMODTT

What it does. Tunes DRAM termination based on read and write margins. The full set of DDR5 RTT settings searched by a particular BIOS has not been disclosed. DISABLED skips this tuning stage; termination itself continues to operate.

Practical choice. AUTO with automatic RTT settings. Test ENABLED if training results are inconsistent; DISABLED if the stage overrides manually tuned RTT settings or makes the result worse.

Max RTT_WR

What it does. Sets the upper limit for automatic RTT_WR tuning in power training. Options: ODT OFF and 120 Ohms. The final RTT_WR is selected during training within this limit.

Practical choice. BIOS DEFAULT VALUE. Test 120 Ω separately. ODT OFF sets the RTT_WR search limit here; DIMM termination as a whole remains active.

DIMM RON Training — DIMMRONT

What it does. Tunes the DRAM driver’s output resistance during reads: memory → CPU. RON applies to the transmitter, RTT to termination.

Practical choice. AUTO. Test DISABLED with manual DRAM Output Driver Impedance if training interferes with it. If only RTT or CPU Write Drive Strength is being changed, the DIMM RON Training mode can remain as it was.

Read ODT Training — RDODTT

What it does. Tunes the CPU receiver’s termination during reads. DIMM RTT_NOM_RD sets termination on the memory side and is tuned separately. On Z890, CPU receiver termination training is split into Read DQ ODT Training and Read DQS ODT Training.

Practical choice. AUTO. Test DISABLED for manually tuned CPU Read ODT if the stage changes the result, or if automatic tuning repeatedly produces poor results. On Z890, compare DQ and DQS separately.

DIMM CA ODT Training — DIMMODTCA

What it does. Tunes command/address line termination on the DRAM side. The older code handles LPDDR4; the scope for DDR5 CA/CS/CK has not been disclosed. CA ODT Optimization is listed separately on Z890.

Practical choice. AUTO. Test DISABLED with manual CA ODT if this stage interferes with it.

Write Drive Strength/Equalization 2D — WRDSEQT

What it does. Jointly tunes CPU driver strength and write equalization: CPU → DRAM. The two dimensions are Drive Strength × Tx Equalization.

Practical choice. AUTO; test ENABLED if training results are inconsistent. DISABLED when manually tuning these parameters if the stage interferes with them. Write Drive Strength and Write Equalization are listed separately on Z890.

Write Slew Rate Training — WRSRT

What it does. Tunes the slew rate of CPU write signals.

Practical choice. AUTO. Test DISABLED with manual Write Slew Rate or if the pass makes the result worse.

Write Driver Strength Training — WRDS

What it does. Trains CPU write driver strength separately. The order and interaction of WRDS and WRDSEQT in the BIOS have not been disclosed.

Practical choice. AUTO. Test DISABLED if training overrides manual CPU Write Drive Strength. On Z890, the field with the corresponding name is Write Drive Strength.

Write Drive Strength Up/Dn independently — WRDSUDT

What it does. Separately tunes the pull-up and pull-down sides of the CPU write driver. DIMM Pull-up / Pull-down Output Driver Impedance applies to the driver on the memory module.

Practical choice. AUTO. Test DISABLED with manual CPU Drive Up/Dn settings or if training produces a poor result.

Read Equalization Training — RDEQT

What it does. Tunes the CPU receiver’s equalizer based on read timing and voltage margins. In the older MRC, the available settings depend on the receiver mode; the code includes CTLE and DFE.

Practical choice. AUTO. At a borderline overclock, test ENABLED separately if results differ between training runs. DISABLED if automatic tuning produces a poor result or when manually tuning the corresponding equalization.

Key detail. On Z890, Read CTLE Training is listed separately from Read Equalization Training.

Read Amplifier Training — RDAPT

What it does. In the older code, tunes the bias current or load of the CPU receiver’s analog circuitry, depending on the mode. It considers read margin and, in the relevant mode, power consumption.

Practical choice. AUTO. At the overclocking limit, test DISABLED separately if there are repeatable signs of poor receiver-mode tuning. ENABLED allows tuning of the already active amplifier’s operating mode. The amplifier’s operating parameters are determined by the tuning result.

Key detail. This option is not listed in the Z890 manual reviewed.

Comp Optimization Training

What it does. In the older MRC, moves the shared portion of byte-group corrections into global compensation, reducing local offsets while aiming to preserve the overall result. Handles Write Drive Strength, Read ODT, and, in some branches, Slew Rate.

Practical choice. AUTO. Test DISABLED if this stage causes problems or when investigating manual compensation offsets. This stage can remain enabled with manual RTT or Drive Strength settings. Hardware compensation also works when training is disabled.

Key detail. Z890 lists Comp Optimization and Pre Training Comp Calibration separately.

TxDqTCO Comp Training — TXTCO

What it does. Tunes delay compensation for the DQ output path during writes: CPU → DRAM. The older MRC evaluates the write window.

Practical choice. AUTO; test ENABLED separately when training results are inconsistent, and DISABLED when this stage reproducibly makes them worse.

ClkTCO Comp Training — CLKTCO

What it does. Tunes delay compensation for the CLK output path. The older code evaluates the command window and also updates the CMD/CTL TCO codes; the exact scope of the current stage has not been disclosed.

Practical choice. AUTO. ENABLED can be tested when training is marginal.

TxDqsTCO Comp Training — TXTCODQS

What it does. Tunes delay compensation for the CPU-side write DQS output strobe.

Practical choice. AUTO, if available. Test DISABLED only when this stage causes a specific deterioration. No separate entry is listed in the Z890 manual reviewed.

VccDLL Bypass Training — VCCDLLBP

What it does. ENABLED allows testing the VccDLL power-supply bypass mode from VccIOG. Whether Bypass is entered depends on the test result; the DLL continues to operate.

Practical choice. AUTO. DISABLED is a diagnostic option if this stage causes problems. The setting is not listed in the Z890 manual reviewed.

PanicVttDnLp Training — PVTTDNLP

What it does. In the older MRC, tunes VttPanicCompDnLPMult for the pull-down branch of fast VTT correction, only for LPDDR with VTT termination.

Practical choice. AUTO. The setting is not listed in the Z890 manual reviewed.

Read Vref Decap Training — RDVREFDC

What it does. Tunes the programmable RxVref decoupling capacitances in the CPU receiver. The older code then provides for RxVref recentering.

Practical choice. AUTO; test ENABLED when read training results are inconsistent, and DISABLED when this pass makes them worse.

Vddq Training — VDDQT

What it does. The older, partly unfinished MRC describes tuning CPU TX VDDQ through FIVR based on command and write margins, only for LPDDR4/5. The role of this stage in controlling DRAM VDDQ through the PMIC remains unknown.

Practical choice. AUTO. With manual CPU TX VDDQ, test DISABLED separately if you suspect interference from this pass. If only DRAM VDDQ is set manually, you can retain the initial mode for this stage. My example in §5.5 applies only to the specified configuration.

Duty Cycle Correction Training — DCC

What it does. Calibrates the correction of high and low durations in the CPU memory interface.

Practical choice. AUTO. When explicitly controlling training stages, start with ENABLED; test DISABLED if a training problem is reproducible.

Key detail. The exact scope of the general Apex switch has not been disclosed. Z890 separately lists Downstream, QCLK Calibration, Rise/Fall, and Functional DCC for DDR5 DQS, DDR5 CLK, and Data DQ.

Periodic DCC

What it does. Allows periodic updates to duty cycle correction after the initial calibration. The interval and conditions for running it on DDR5 Apex have not been published.

Practical choice. AUTO. When selecting a mode explicitly, use DISABLED as the baseline for comparison; test ENABLED separately, including extended operation and transitions between idle and load.

Key detail. The setting appears in the Z790 E22758 manual; it is not listed in the earlier E21287 or in the Z890 E25061 manual.

Tx Dqs Dcc Training — TXDQSDCC

What it does. Tunes duty cycle correction for the CPU-side write DQS output strobe, for transfers from CPU → DRAM.

Practical choice. AUTO; when selecting a mode explicitly, start with ENABLED. Test DISABLED if this stage reproducibly makes the result worse.

Key detail. No separate entry is listed in E25061; a connection to Functional DCC for DDR5 DQS has not been confirmed.

Round Trip Latency — RTL

What it does. Optimizes the latency of data returning after a read command. In the older Ice Lake MRC, RTL is tuned together with receive FIFO delays, with read-window checks and a margin.

Practical choice. ENABLED. I always leave this stage enabled when tuning memory manually.

Key detail. Initial RTL values are already calculated during Receive Enable Training; a separate pass optimizes them. RTL is not listed in E25061. It is unknown whether the Read/Write Rank-to-Rank Training settings replace RTL.

Turn Around Timing Training — TAT

What it does. Tunes the intervals for read → read, read → write, write → read, and write → write, including rank changes. The older MRC optimizes the corresponding variants of tRDRD, tRDWR, tWRRD, and tWRWR, as well as CPU receiver ODT turn-on timing and duration.

Practical choice. DISABLED. I tune memory and tertiary timings manually, so I disable automatic tuning.

Key detail. The older MRC also tunes ODT with a single rank. TAT is retained on Z890.

DIMM DFE Training — DIMMDFE

What it does. Trains Decision Feedback Equalization in the DRAM receiver during writes: CPU → memory. DFE accounts for previous bits and compensates for their effect on detecting the current bit.

Practical choice. AUTO. When explicitly controlling training stages, start with ENABLED; test DISABLED if training reproducibly produces poor results or when tuning DIMM DFE manually.

Key detail. Hardware DFE may also operate when training is disabled.

EARLY DIMM DFE Training — EARLYDIMMDFE

What it does. A separate early pass for tuning DRAM DFE. The exact search sequence and interaction with the main DIMM DFE stage in Apex BIOS have not been disclosed. It is unknown whether one pass can replace the other.

Practical choice. AUTO. Compare ENABLED and DISABLED separately for a specific training problem.

DRAM EMPHASIS Training — DRAMEMPHASIS

What it does. The purpose of this switch for DDR5 in Apex BIOS has not been disclosed.

Practical choice. AUTO.

DRAM DCA Training — DRAMDCA

What it does. Trains the Duty Cycle Adjuster inside DRAM: adjusts the high and low durations of the DQ/DQS outputs during reads, memory → CPU. The goal is to reduce duty cycle distortion, bringing the durations closer to 50/50.

Practical choice. AUTO. When explicitly controlling training stages, start with ENABLED; test DISABLED if training reproducibly gets worse.

DQS OFFSET ADJUST Training — DQSOFFSETADJUST

What it does. The implementation of this pass in Apex BIOS has not been disclosed. DDR5 provides Read DQS Offset Timing through MR40: the DQS strobe starts transmitting earlier relative to DQ. A connection between this switch and MR40 has not been confirmed.

Practical choice. AUTO. Compare ENABLED/DISABLED separately for a specific training problem.

Key detail. According to the DRAM documentation, changing MR40 leaves data transmission timing and Read Latency unchanged.

Rank Margin Tool Per Bit — RMTBIT

What it does. Measures timing and receiver-threshold margins for individual DQ bits. In the older MRC, a separate flag starts it without checking the RMT flag; the dependency in current ASUS BIOS implementations has not been disclosed.

Practical choice. AUTO or DISABLED if the results are not used; ENABLED for diagnostics when the data is accessible.

Rank Margin Tool — RMT

What it does. Evaluates timing and Vref margins for reads, writes, and commands. Allows comparison of trained states.

Practical choice. AUTO or DISABLED for normal operation; ENABLED if you have a way to read the results. BDAT export is enabled separately. The report may still be unavailable in the BIOS interface.

Memory Test — MEMTST

What it does. Tests memory during initialization; ASUS has not disclosed the coverage or patterns.

Practical choice. AUTO; ENABLED for boot diagnostics. No separate entry is listed in E25061 for Z890.

DIMM SPD Alias Test — ALIASCHK

What it does. Intended to detect DRAM address aliasing when the module organization is described incorrectly. The older code checks geometry and capacity against SPD; the physical address test is unfinished.

Practical choice. AUTO or ENABLED. DISABLED makes sense only for a confirmed false positive.

Post Package Repair Training — PPR

What it does. Allows defective DRAM rows to be replaced with spare rows: Soft PPR is a temporary repair; Hard PPR is permanent and survives power loss.

Practical choice. Do not force it on for normal overclocking; when controlling it manually, start with DISABLED. Do not move to Hard PPR because of errors that occur only when overclocked.

Key detail. The repair type and trigger conditions may be set separately. The repair type used by ASUS has not been established; the Z890 menu name omits Training.

Retrain Margin Check — RMC

What it does. In the older MRC, checks read, write, and command margins; if margin is insufficient, raises the optimization thresholds and requests retraining during the current initialization. Execution also depends on the power training mode.

Practical choice. AUTO. ENABLED for investigating inconsistent training results; DISABLED if the check itself causes a problem.

Margin Check Limit

What it does. Selects the margin check used to decide whether to retrain on the next boot: DISABLED, L1, L2, BOTH.

Practical choice. DEFAULT VALUE. For diagnostics, start with L1; test L2 and BOTH with the L2 scaling in mind.

Margin Limit Check L2

What it does. Sets the threshold: L2 = L1 × value / 100. Available when L2 or BOTH is selected.

Practical choice. DEFAULT VALUE; use 100 for comparison.

Key detail. A higher value sets a stricter check threshold. A range of 1–300 is specified for Z790; the Z890 manual does not give the limits.

CA ODT Optimization

What it does. Separate optimization of command/address line termination. DIMM CA ODT Training is also retained in the menu; ASUS does not describe how the tasks are divided between these two stages.

Practical choice. AUTO. When tuning manually, change these two settings separately.

Unmatched Write Time Centering 1D — UNMATCHEDWRTC1D

What it does. A separate one-dimensional write alignment stage for the Unmatched path. The public Intel interface does not disclose how it differs from regular Write Timing Centering 1D.

Practical choice. AUTO.

RxVref Per-Bit Training — RXVREFPERBIT

What it does. Tunes the input detection threshold separately for each data bit on the CPU receiver side.

Practical choice. AUTO.

DDR5 ODT Timing Config — DDR5ODTTIMING

What it does. A separate stage for tuning DDR5 ODT timing: when termination turns on and off relative to data transfers.

Practical choice. AUTO. Compare ENABLED and DISABLED separately for a reproducible problem during full training.

Read CTLE Training — RDCTLET

What it does. Tunes the CPU receiver linear equalizer. CTLE adjusts the frequency response of the input path, reducing signal distortion during reads.

Practical choice. AUTO.

Ddr5 Rx Cross-Talk Cancellation — DDR5XTALK

What it does. Controls crosstalk compensation in the DDR5 receive path: adjacent lines can induce interference in the received signal.

Practical choice. AUTO.

Unmatched Rx Calibration — RXUNMATCHEDCAL

What it does. Calibrates the Unmatched receive path. Its architecture and adjustable quantities have not been disclosed in the ASUS manuals or the public FSP interface.

Practical choice. AUTO.

DQ/DQS Swizzle Training — DQDQSSWZ

What it does. Configures the mapping of logical DQ/DQS lines to their physical routing, accounting for line swaps.

Practical choice. AUTO.

Write DQ/DQS Retrain — WRTRETRAIN

What it does. Controls a separate stage that retunes the relative alignment of DQ and DQS during writes. The older MRC describes such a mechanism for LPDDR; its DDR5 implementation on Z890 has not been disclosed.

Practical choice. AUTO.