pxtech

Search the site

    Colour theme
    DDR5 GUIDE INTEL LGA1700 / LGA1851PDF · pages 4–7Pages 4–7

    CONTENTS

    The chapters progress from DDR5 fundamentals and platform selection to manual tuning, memory training and stability testing. Chapter 11 collects the formulas; Chapter 03 explains the timings in detail.

    Introduction

    Who this manual is for and how to use it

    1. 1.1Approach and limits of evidence
    2. 1.2Who this manual is for and how to use it

    DDR5 fundamentals and platform selection

    From JEDEC standards and DIMM architecture to board topology and CUDIMMs

    1. 2.1WHAT EXACTLY ARE WE OVERCLOCKING?
    2. 2.2IMC: MEMORY CONTROLLER
    3. 2.3JEDEC, MT/s, AND VOLTAGES
    4. 2.4SPD AND INTEL XMP 3.0
    5. 2.5PMIC — POWER CONTROL ON A DDR5 MODULE
    6. 2.6Ranks, x8/x16, and density
    7. 2.7KIT CAPACITY AND IMC LOAD
    8. 2.8FROM DDR3 TO DDR5: GENERATIONS AND DIMM DESIGN
    9. 2.8.1PCB sides and ranks in DDR5: clarification
    10. 2.8.2DRAM IC: DIE AND PACKAGE
    11. 2.9MANUFACTURER, DENSITY, AND REVISION
    12. 2.10XMP BINNING AND KIT SCREENING
    13. 2.11DPC/SPC, MODULES, AND ROUTING TOPOLOGY
    14. 2.12CHOOSING AN LGA1700 MOTHERBOARD: Z690 AND Z790
    15. 2.13LGA1851, Z890, AND CUDIMM
    16. 2.14MAXSUN Z690-Z890 1SPC BOARDS
    17. 2.15MOTHERBOARD CLASSIFICATION
    18. 2.16PRACTICAL PLATFORM AND KIT SELECTION

    Timings

    Purpose, formulas, dependencies and the ASUS BIOS map

    1. 3.1How to read timings
    2. 3.2The ACT - RD/WR - PRE command sequence
    3. 3.3Primary timings
    4. 3.4Secondary timings: activation and bank groups
    5. 3.4.1tFAW: where the minimum comes from
    6. 3.5Secondary timings: reads, writes, and recovery
    7. 3.6Secondary timings: refresh
    8. 3.6.1Secondary timings: calculating tREFI/tRFC
    9. 3.7Tertiary timings: command transitions
    10. 3.8Maintenance and power-saving timings
    11. 3.9Correlations: rank, density, capacity, ICs and practical tCL/VDD
    12. 3.10ASUS Z790 Apex Encore BIOS 2202
    13. 3.11ASUS Z890 Apex: what changed

    Voltages

    Power rails, their interactions and diagnostics

    1. 4.1The DDR5 power map
    2. 4.2CPU System Agent Voltage
    3. 4.3CPU VDDQ TX
    4. 4.4Memory Controller Voltage / VDD2
    5. 4.5DRAM VDD and DRAM VDDQ
    6. 4.6VPP, PMIC, and SPD Hub
    7. 4.7Voltage relationships and the sweet spot
    8. 4.8ASUS Z790/Z890: exact setting names
    9. 4.9Voltage ranges and the effects of cooling

    Memory training and the tuning process

    What MRC does and how to progress from a baseline to a daily profile

    1. 5.1Preparation and a clean baseline
    2. 5.2Where to start tuning
    3. 5.3What memory training is
    4. 5.4Boot types and saved data
    5. 5.5ASUS Z790 Training Algorithms
    6. 5.6ASUS Z890 Training Algorithms
    7. 5.7RTL/IOL training
    8. 5.8What changed on Z890: CUDIMM, CKD, and DIMM Fit
    9. 5.9DDR5 resistances: ODT, RTT, and RON
    10. 5.10Profiles and recovery

    ADVANCED ANALYSIS OF TRAINING ALGORITHMS

    Purpose of 87 settings, practical choices and Z790/Z890 specifics

    1. 6.1Command/Address Path Tuning
    2. 6.2Initial Read Training
    3. 6.3Write Training
    4. 6.4Read Training
    5. 6.5ODT, RON, and Transmitter Drive Strength
    6. 6.6Receiver Equalization
    7. 6.7PHY compensation and calibration
    8. 6.8Duty cycle correction — DCC
    9. 6.9RTL and transitions between operations
    10. 6.10DDR5 signaling
    11. 6.11Signal margins, checks, and repair
    12. 6.12Additional Z890 Apex algorithms

    Stability-testing tools

    Independent workloads, pass criteria and a practical stopping point

    1. 7.1What needs to be demonstrated
    2. 7.2y-cruncher: component workloads
    3. 7.3Karhu RAM Test
    4. 7.4TestMem5 / TM5
    5. 7.5MemTest86 Free / Pro
    6. 7.6RAM Test Pro
    7. 7.7Additional tools
    8. 7.8Recommended test combinations and duration
    9. 7.9Diagnosing errors and deciding when a profile is ready

    Performance tests and monitoring

    Measuring results, recording conditions and interpreting sensors

    1. 8.1What a benchmark actually measures
    2. 8.2AIDA64 Extreme
    3. 8.3CPU-Z: settings and SPD
    4. 8.4HWiNFO: monitoring
    5. 8.4.1HWiNFO: the Memory Timings window
    6. 8.5ASRock Timing Configurator
    7. 8.6pyhwinfo: low-level memory and IMC settings
    8. 8.7ASUS MemTweakIt
    9. 8.8Current alternative benchmarks
    10. 8.9A consistent comparison protocol

    Software: websites, downloads and manuals

    Stability tests, benchmarks, monitoring, and timing snapshots

    Additional considerations

    Factors affecting stability beyond the timing table

    1. 10.1DIMM cooling and thermal stability
    2. 10.2Socket, mounting pressure, and IMC variation
    3. 10.3BIOS, MRC, and reproducibility
    4. 10.4Data integrity and a safe environment
    5. 10.5Synthetic tests and real-world performance
    6. 10.6Daily, benchmark, and screenshot profiles
    7. 10.7Four DIMMs and high capacities
    8. 10.8Reference materials for reproducing a configuration
    9. 10.9Sources and the revision history

    Formulas

    Primary, secondary, tertiary, and maintenance timings; empirical RTL guideline

    Glossary

    Expanded abbreviations and explanations of the manual’s terminology

    1. 12.1Standards, platform, and controller
    2. 12.2Modules, organization, and topology (continued)
    3. 12.3Commands, buses, and signal paths
    4. 12.4Primary, secondary, and tertiary timings
    5. 12.5Refresh and maintenance intervals
    6. 12.6Voltages and power domains
    7. 12.7Termination and signal integrity
    8. 12.8Training, booting, and recovery
    9. 12.9Profiles, errors, and stability
    10. 12.10Tools, workloads, and metrics
    11. 12.11ADVANCED TRAINING ALGORITHMS

    Documentation consulted

    Standards, datasheets, and manuals used as the basis for this manual

    1. 13.1TRAINING ALGORITHMS: sources