Timings

A timing specifies a duration or an interval between memory events. Most are minimums; tREFI limits the average interval between refreshes. BIOS values usually use DDR5 clock cycles, so their duration depends on data rate. BIOS menus and the community group timings into primary, secondary and tertiary parameters.

FIRST CONVERT CLOCK CYCLES TO NANOSECONDS

FOUR TYPICAL ACCESS PATHS

Conversion when changing data rate: Nnew = Nold × MT/snew / MT/sold. Round up for minimum intervals; round down for the maximum interval tREFI. Example: tRFC 688 at DDR5-8200 -> 688 x 8400 / 8200 = 704.78 -> 705 cycles at DDR5-8400. Nold is the original value; round a fractional tREFI result down.

Primary timings describe opening a row, accessing data, and preparing a bank for the next row. They form one sequence, but are not calculated from one another by a simple rule: tCL, tRCD, and tRP are limited by different internal IC operations.

WHY THE DDR5 PRIMARY TIMING STRING LOOKS DIFFERENT

HOW TO UNDERSTAND THE RELATIONSHIP WITHOUT INVENTING A FORMULA

Lowering tCL reduces latency after the READ command has already been issued, but does not open the row any faster. A good tCL therefore does not force tRCD or tRP to fall with it. On Hynix DDR5, tCL often continues to respond to VDD after tRCD/tRP have reached their own limits. tRAS, by contrast, is validated through the actual row-closing sequence. For an early READ after ACT, the minimum cycle is described by the greater of tRAS and tRCDRD+tRTP, plus tRP. If the sum exceeds tRAS, reducing tRAS alone does not speed up the cycle.

For the baseline profile with an early READ after ACT: read from a closed row = 49 + 36 = 85 CK; row conflict = 49 + 49 + 36 = 134 CK; tRAS = 49 + tRTP12 = 61; tRC = 61 + 49 = 110.

* A particular BIOS/MRC version may in fact couple or normalize tRCDRD and tRCDWR in a certain

mode; however, public documentation does not confirm any universal requirement that they be equal.

DDR5 divides banks into groups. Two commands to different groups can usually be issued closer together than within the same group because internal resources conflict less. S therefore means the short path and L the long path; in Intel tertiary timings, dg and sg follow the same logic.

* Details in 3.4.1

WHERE THE BENEFIT APPEARS

tRRD and tFAW have the greatest effect in workloads that open rows in different banks concurrently. Their effect is barely visible during a short sequential read from an already open row. tCCD, by contrast, determines the spacing of adjacent column commands and is more noticeable in a sustained data stream. With tRRD_S=8, consecutive ACT commands can occur at 0, 8, 16, and 24 CK, with the fifth no earlier than 32 CK. This is how tRRD_S=8 and tFAW=32 work together. A value above 32 further restricts the activation stream. For the x16 devices considered here, with a 2 KB page, the cycle-based portion of tFAW is 40 CK; the time limit also depends on the datasheet and speed bin. Server 3DS memory has additional constraints. tRRD_L needs both 8 CK and the minimum in ns.

tFAW specifies the minimum time from the first to the fifth ACT command within one rank. The check repeats for every new command: ACT5 is compared with ACT1, ACT6 with ACT2, and so on. tRRD must also be met between adjacent ACT commands.

WHY 8 NS IS NOT A UNIVERSAL LIMIT

The tFAW minimum is specified simultaneously in CK cycles and nanoseconds. Both limits come from the table for the required DRAM organization and speed bin. One limit cannot be applied to all DDR5: the time component changes between bins, while the cycle component also depends on device organization.

The table contains selected speed bins for SK hynix 32 Gbit M-die, x8, with a 1 KB page. Minimums come from the datasheet. The green 8200 row is my OC profile: it lists the 32 CK setting and its time calculated from frequency.

WHY THE PRACTICAL MINIMUM FOR x8 IS 32 CK

tFAW (Four Activate Window) permits no more than four ACTIVATE commands within one rank in its window. tRRD_S specifies the interval between adjacent ACT commands to different bank groups. For standard DDR5 x8 with a 1 KB page, the minimum limit considered here is tRRD_S = 8 CK.

There are four intervals between ACT1 and ACT5: 4 x tRRD_S = 4 x 8 = 32 CK. tRRD_S prevents ACT5 from being issued earlier; the figure shows the densest possible ACT sequence while meeting the other constraints.

Estimated ACT-command density at the specified tRRD_S.

PAGE SIZE: WHY THE LIMIT FOR x16 IS 40 CK

DDR5 x4/x8 uses a 1 KB page; x16 uses 2 KB. For x16, the cycle-based tFAW minimum is 40 CK even though tRRD_S may also be 8 CK: 4 x 8 = 32 CK. The value 40 is not derived from 4 x tRRD_S: the larger activated page requires a stricter window for a series of ACT commands and a tighter peak-load limit. tFAW is the constraint here: ACT5 can occur no earlier than 40 CK, not 32 CK.

JEDEC: BOTH CK AND NANOSECONDS COUNT

Here nCK is the duration of the stated number of cycles: times are compared. 32/40 CK are cycle limits; the minimum in ns comes from the specific IC and speed bin, so the final value is not always equal to 32/40 CK.

tRTP, tWR, and tWTR start from different events. To calculate the complete command-to-command path, add the preceding delays. This teaching example uses 8200 MT/s and CL36 with the SK hynix 32 Gbit 8000 speed bin. All sums are in clock cycles (CK).

READ AND WRITE: WHEN THE ROW CAN CLOSE

Read. tCL runs from READ to the first data; tRTP runs from the same READ to permitted row closure (PRE). Do not add CL and RTP for this interval. For 7.5 ns: 7.5 × 8200 / 2000 = 30.75 → 31; select tRTP32 from the MR6 table. My overclocking profile uses tRTP12, or 14 at high data rates; I do not go below 12.

Write. tCWL runs to the first data, then the BL16 burst takes 16 / 2 = 8 cycles, followed by tWR recovery after the data ends. DRAM tCWL = tCL − 2 = 34. For tWR = 30 ns, the calculation gives 123, then the permitted MR6 code 126. In our overclocking profile, tWR = 48, with no further reduction.

WRITE → PRE: tCWL + 8 + tWR = 34 + 8 + 126 = 168. For a WRITE followed by a READ with auto-precharge in the same bank, tCCD_WTRA ≥ 168 − tRTP32 = 136. Subtract RTP because PRE waits that interval after READ.

WTR: THE WAIT AFTER WRITE DATA ENDS

tWTR_S applies to another bank group: for this speed bin, compare 4 cycles and 2 ns → 8.2 → 9. tWTR_L covers the long path within the same group: 16 cycles or 10 ns → 41. These values come from the specific IC speed bin, not CL.

DRAM WRITE to READ: tCWL + 8 + tWTR. Across groups: 34 + 8 + 9 = 51; for the long path within one group: 34 + 8 + 41 = 83. The separate path to another bank in the same group (M) may be shorter in the datasheet; do not automatically substitute it for L.

In an overclocking profile, WTR, WR and RTP are tightened below datasheet intervals and tested under load.

WHY INTEL tWRRD IS NOT THE COMPLETE DRAM SUM

tWRRD = write → read; tRDWR = read → write. WTR uses the first group. S corresponds to dg, different bank groups; L corresponds to sg, the same group. Intel stores scheduler intervals; the utility derives WTR from them.

In pyhwinfo's main calculation for Raptor Lake DDR5 ≥ 5200: WTR_S = WRRD_dg − C − 10 − B; WTR_L = WRRD_sg − C − 10 − B. C is the controller's read-back CWL field. B is MR8[7]: 0 for the short, 1 for the long write-signal ending. Do not substitute its duration of 0.5 or 1.5 cycles for this bit.

Example: C34, B1, WRRD_dg54, WRRD_sg86. This gives S = 54 − 34 − 10 − 1 = 9, L = 86 − 34 − 10 − 1 = 41. The 10 = burst 8 + decoder correction 2. This is a specific utility's display calculation; read C and B rather than guessing them from CL.

HOW THE LINKED PAIR CHANGES

With C and B fixed, WRRD_dg54 → 55 gives WTR_S9 → 10; sg changes only the long pair. To keep WTR unchanged when C rises by 2, increase WRRD by 2 as well. Check the values actually applied after training.

The separate DEC/ADD branch and reverse calculation are explained in 3.7; compact formulas are in Chapter 11, p. 89.

DRAM cells gradually lose charge, so memory must be refreshed regularly. tRFC specifies the duration of one refresh cycle, while tREFI specifies the average interval between cycles. The controller can shift individual refresh commands slightly. Lower tRFC and higher tREFI reduce idle time, but also reduce thermal margin.

REFERENCE REFRESH SPECIFICATIONS BY MODE AND DIE DENSITY

NORMAL REFRESH: TEMPERATURE AND INTERVAL

SPECIFIED AND ACTUAL TEMPERATURE ARE NOT ONE NUMBER

The 85 °C threshold refers to TCASE, the case temperature of the DRAM IC itself. On consumer DDR5, HWiNFO usually shows a local SPD Hub/PCB sensor: this is a useful monitoring point, but not the temperature of the hottest IC and not the TCASE from the specification.

With tREFI above approximately 30000, directed airflow is a mandatory testing condition under this manual's methodology, but a fan does not replace monitoring. If the profile is stable only with directed airflow, the same airflow must be used in daily operation. The 47 °C / 131071 example above characterizes my specific kit, voltages, and test, not a limit for all DDR5.

Additional ranks and ICs usually increase cooling requirements.

The tREFI and tRFC values in BIOS are expressed in memory clock cycles, so the same value at two data rates represents different amounts of time. tREFI limits the maximum average interval between refreshes, while tRFC specifies the minimum duration of a refresh cycle. This is why they are rounded in opposite directions.

tREFI: A NOTIONAL LADDER FROM LOWER TO HIGHER

PRACTICAL tRFC AND tRFCsb/tRFCpb TUNING

For Hynix in FGR, the guideline is tRFCpb ≈ tRFC2 − 30 ns: at 8200, RFC2 − 123 cycles (688 → 565). The tRFC field must mean tRFC2; this is an empirical estimate, not a formula from tRFC1. Tune tRFC first, then test tRFCpb separately; raise tREFI only after restoring margin.

* JEDEC defines tRFC1/tRFC2 by refresh mode; separate tuning is not always available. Here, tRFC is the controller's runtime

value. Equal BIOS numbers do not prove equal JEDEC specifications.

** JEDEC tRFCsb/REFsb and Intel tRFCpb/REFpb belong to different documentation layers. Their practical correspondence

depends on the controller and BIOS; they are not universal synonyms and neither is tRFC2.

Intel tertiary timings describe transitions between commands. All intervals below are in memory clock cycles. For each formula, first identify the direction, then the bank path and the utility's calculation method.

DIRECTION AND BANK PATH

RDRD - read → read; WRWR - write → write; RDWR - read → write; WRRD - write → read. WTR uses WRRD. S ↔ dg - different bank groups; L ↔ sg - the same group. The path to another bank within a group may be shorter than the overall long path L.

dr — another rank on the same DIMM: used with 2R. dd — another DIMM in the channel: used with 2DPC. With 1R/1DPC, neither path is used. Start with Auto; these timings cannot be derived from CL.

For BL16: RDRD_dg = WRWR_dg = 8. The physical references for sg differ: RDRD uses tCCD_L; WRWR uses tCCD_L_WR2 or tCCD_L_WR, depending on the write path.

WHY THE DDR4 FORMULA READS FOUR HIGHER

A DDR4 BL8 burst takes 4 cycles; a DDR5 BL16 burst takes 8. The base reverse calculation therefore changes: WTR_L = WRRD_sg − CWL − 10; WTR_S = WRRD_dg − CWL − 10; WR = WRPRE − CWL − 8. The 10 includes burst 8 and decoder correction 2.

If a program still subtracts 6 for WTR or 4 for WR, the same input fields produce a result 4 higher. Without additional corrections: CWL34, WRRD_sg64/dg52, WRPRE90 → L20/S8/WR48; the old formulas give 24/12/52.

In anta777's October 31, 2022 analysis, ASRock Timing Configurator is described as subtracting 6 for WTR, and ASUS MemTweakIt as subtracting 4 for WR; MSI Dragon Ball uses the base DDR5 relationships. ASRock calculates WR correctly there. This describes those versions, not a rule that 'all ASRock values are always +4.' Check the utility version and platform separately.

CORRECTIONS TO THE BASE CALCULATION

In pyhwinfo's main calculation on Raptor Lake DDR5 from 5200: WTR = WRRD − C − 10 − B. C is the read-back controller CWL field, not automatically CL−2. B is MR8[7]: 0 for the short, 1 for the long write-signal ending. It is a setting bit, not its duration of 0.5/1.5 cycles.

With C34, B1: dg54 → S9; sg86 → L41. In reverse: WRRD = C + 10 + B + WTR. With C and B fixed, WRRD +1 gives WTR +1; if C rises by 2, the same WTR needs WRRD +2.

For WR, the code starts with WRPRE − C − 8, then adds 1 with 2N. Another calculation: WR = WRPDEN − C − 9. Thus, WRPDEN=WRPRE+1 is valid only without this correction; with it, the difference is 2.

A separate DEC/ADD branch: C′ = C − DEC_tCWL + ADD_tCWL; WTR_alt = WRRD − C′ − 10. It does not subtract B. With C34/DEC2/ADD0 and dg54, the result is 12. Do not combine these branches into one sum of corrections.

READ → WRITE AND PRACTICAL VALIDATION

DRAM READ→WRITE interval = CL − CWL + 8 + 2 − O + (P − 0.5) + W. O is the read-signal offset; P is the duration of its ending; W is the write-signal preparation time. CL36/CWL34 with O0/P1.5/W4 gives 17. BIOS tRDWR also accounts for the controller and training.

Compare the applied fields and the utility's calculation method, then validate under load and with cold boots. The main WTR explanation is in 3.5; compact formulas are in Chapter 11, p. 89.

These parameters govern exit from idle, self-refresh, signal calibration, and maintenance commands. Tuning them alone rarely provides a measurable performance gain, but an excessively tight value can break cold boot, sleep, wake, or training repeatability.

monolithic DDR5 (DDR5 devices with a single DRAM die per package).

POWER POLICIES ARE NOT A SINGLE TIMING

WHAT TO TEST BESIDES A MEMORY TEST

A daily profile must withstand not only sustained load but also transitions: a cold boot after complete power removal, several restarts, extended idle, sleep, and wake. This is where tXP, tXS, and power-state entry intervals are used.

If an error appears only after sleep, first return service intervals and power policies to Auto, then repeat the same scenario. This A/B test separates a power-state problem from cell instability more quickly.

The same capacity does not mean the same behavior. Limits are affected by IC density and revision, rank count, modules per channel, and screening quality. Determine the kit's physical organization first; only then transfer timing logic.

TYPICAL KITS AND TUNING PRIORITIES

CAPACITY MATTERS THROUGH ORGANIZATION

A 24 GB module built with 24-Gbit ICs remains single-rank, while a 48 GB module using the same ICs usually requires two ranks. In the latter case, the controller gains more parallelism but must also switch ranks and train additional dr paths.

When moving from 48 GB to 96 GB, retest frequency, tertiary transitions and refresh, even with the same IC revision.

CUDIMM improves the clock path through CKD, but does not change the meaning of tCL, tRCD, tRFC, or tertiary transitions. When transferring a profile, preserve relationships and time in ns, not absolute values.

In this chapter, I use the ASUS ROG Maximus Z790 Apex Encore with BIOS 2202 as the reference. The official manual confirms the overall structure, but the individual entries depend on firmware, processor, and modules. Setting names are given exactly as ASUS labels them.

MAP OF THE DRAM TIMING CONTROL SECTION

EXACT FIELDS MOST OFTEN SET MANUALLY

WHAT TO RECORD BEFORE MANUAL ENTRY

After full training, save the frequency, Gear, Command Rate, all primary and secondary timings, the tRDRD/tWRWR/tRDWR/tWRRD groups, module temperature, and BIOS version. For fields with Training/Runtime, record Runtime specifically.

After startup, the MRC may round an entered value to a valid code or apply an internal constraint. Use the actual post-boot value as your reference.

The meaning of the main DDR5 timings has not changed on Z890, but ASUS reorganized the menu for Core Ultra 200S, CUDIMM, and the new MRC. Transfer the logic and relationships from Z790, not every number or field name. The table is based on the public ROG Z890 manual; the specific entries depend on BIOS, CPU, and DIMM.

NEW AND HIDDEN FIELDS

WHAT TO TRANSFER FROM Z790 AND WHAT TO FIND AGAIN

You can transfer the meaning of settings, the tRC=tRAS+tRP formula, the tRRD/tFAW and tWTR/tWRRD relationships, and the approach of converting cycles to nanoseconds from Z790. Frequency, voltages, training results, and PHY-dependent values must still be found again. Do not search for Z890 entries absent from the public manual under similar names and fill them with Z790 numbers. Start with Auto and the actual value, then confirm the function for the specific BIOS version. Leave Divide DRAM timings on Auto until a field-range limitation appears. It has no universal 9600 MT/s threshold: the BIOS/MRC decides according to frequency and the encoding of the specific timing.

* For Raptor Lake-S, public Intel documentation states that DDR5 RFM is not enabled. The presence of a similar BIOS entry alone

does not prove that the mechanism is active on a specific platform.