DDR5 fundamentals and platform selection

DDR5 overclocking means tuning the entire chain from the memory controller in the processor to the DRAM cells. Increasing Memory Frequency places greater demands on the entire signal path: the CPU socket, motherboard traces and DIMM slot. The interface must then train correctly and reproduce the result at every boot.

THE ENTIRE CHAIN MUST WORK

DATA RATE AND CLOCK FREQUENCY

DDR5-8000 means 8000 million transfers per second on each data pin, or 8000 MT/s. Memory transfers data on both clock edges, so the actual interface clock frequency, fCK, is approximately 4000 MHz. Retailers and utilities often write "8000 MHz," but this manual expresses memory data rate in MT/s.

The theoretical bandwidth of one 64-bit channel, GB/s = MT/s × 8 / 1000. DDR5-6000 provides 48 GB/s; DDR5-8000 provides 64 GB/s. Two channels provide 96 and 128 GB/s, respectively. Actual values are lower because of commands, refresh, bank switching, and controller idle time.

WHY A HIGH CL CAN STILL BE FAST

Timings are expressed in clock cycles, not nanoseconds. Pure CAS latency is calculated as CL x 2000 / MT/s. DDR5-6000 CL30 and DDR5-8000 CL40 therefore both yield 10 ns: the latter uses more cycles, but each cycle is shorter. This is only one part of total latency; tRCD, tRP, IMC queues, Gear mode, processor interconnects, and cache behavior add to it.

CHANNEL, SUBCHANNELS, AND CONTROLLER

A standard DDR5 UDIMM remains 64 bits wide, but is split into two independent 32-bit subchannels. They increase parallelism within a single memory channel; they do not turn one module into a dual-channel system. Two 64-bit CPU channels still require at least two correctly installed modules.

Gear indicates the ratio of the controller-domain frequency to the physical DRAM clock. Gear 1, or 1:1, exists in Intel terminology and remains practically relevant primarily for DDR4. Official Intel operating points for DDR5 on LGA1700 use Gear 2, while LGA1851 uses Gear 2 or Gear 4; Gear 1 is not relevant as a high-frequency DDR5 mode. A higher Gear makes high MT/s easier to achieve, but adds command-path latency.

WHICH GROUPS OF SETTINGS CHANGE IN BIOS

The IMC, or integrated memory controller, is the memory controller built into the processor. It accepts requests, distributes them among channels, ranks, and banks, builds the DRAM command queue, and services refresh. The PHY handles the electrical interface with the memory lines. The MRC within the BIOS operates only during startup: it reads the SPD, configures the IMC/PHY, runs memory training, and leaves behind a working configuration. The MRC is not part of the memory request path during operation.

MEMORY REQUEST PATH

Main stages of a request to DRAM.

TWO CHANNELS, BUT FOUR DDR5 SUBCHANNELS

Raptor Lake-S remains a dual-channel desktop platform. In DDR5 mode, each of memory channels A and B comprises two independent 32-bit subchannels, totaling 64 data bits per channel. With both channels in use, four 32-bit subchannels are available. This is not equivalent to a quad-channel platform with four 64-bit channels.

Intel describes two independent MC blocks, one per memory slice. The practical takeaway for the user is that both channels should be populated symmetrically using the motherboard's recommended slots, while the subchannels allow the scheduler to interleave requests more flexibly.

HOW LOAD LOWERS THE OFFICIAL RATING

Official operating modes for higher-end 13th Gen Intel Core desktop processors. Some CPU models have lower limits; operation above specification is overclocking.

The word "standard" has three different meanings here. JEDEC defines operating modes for the DRAM devices themselves, Intel specifies the official memory-controller limit for a particular processor, and the module manufacturer writes supported parameters to the SPD. A mode is standard for the entire system only when all three layers support it simultaneously.

THREE LAYERS OF COMPATIBILITY

JEDEC SPEED BINS USED IN THIS CHAPTER

This chapter uses JEDEC JESD79-5D v1.41, dated November 2025. It defines DDR5-3200, 3600, 4000, 4400, 4800, 5200, 5600, 6000, 6400, 6800, 7200, 7600, 8000, 8400, 8800, and 9200. The system's operating data rate also depends on CPU, motherboard and module support.

WHAT IS CONSIDERED STANDARD ON OUR PLATFORMS

* In the 14th Gen datasheet, DDR5-5600 for 2R is marked as pending Intel enablement; the product brief still lists DDR5-5200. We therefore do not treat 5600 as an unconditionally available current POR.

NOMINAL DDR5 VOLTAGES

For standard DDR5, the nominal DRAM VDD and DRAM VDDQ values are 1.10 V, while VPP is 1.80 V. However, a manual mode at 1.10 V does not automatically become JEDEC-compliant: the IC speed bin, SPD data, CPU support, and motherboard configuration must all match. XMP often uses higher VDD/VDDQ and tighter timings.

The key notation rule is: DDR5-8000 or 8000 MT/s is correct; "8000 MHz" is common slang. The clock frequency of this interface is approximately 4000 MHz.

WHY JEDEC-8000 CAN STILL BE OVERCLOCKING

The DDR5-8000 speed bin in JESD79-5D means that the standard defines such a mode for compatible DRAM devices. But a DDR5-8000 XMP kit may use its own timings and higher voltages, while the official CPU limit remains 5600, 6400, or 7200 MT/s. For such a system, 8000 MT/s is overclocking regardless of the number 8000 appearing in the JEDEC standard.

POR, or Plan of Record, is the officially supported Intel mode for the specified module and rank configuration. Operation above POR is overclocking.

SPD, or Serial Presence Detect, is a data set stored in the module's nonvolatile memory. In DDR5, the EEPROM is integrated into the SPD Hub. The BIOS reads this data before the operating system starts and uses it as the module's initial description, but the platform itself still builds and trains the final operating mode.

WHAT THE SPD CONTAINS

HOW A PROFILE BECOMES AN OPERATING MODE

XMP 3.0 IS OVERCLOCKING

Intel explicitly calls XMP an overclocking technology. A profile contains a target data rate, a set of specified timings, and voltages validated by the kit manufacturer. XMP 3.0 was created for DDR5 and allows up to five profiles: three factory profiles and two user-rewritable profiles.

I do not recommend using XMP as a ready-made daily profile. Many motherboards apply excessive voltages, calculate Auto values differently, and sometimes train the same kit poorly. It is more reliable to start from a stable baseline, tune the memory manually, and then verify the result.

Before enabling XMP, always compare the kit's exact part number with the QVL for the specific motherboard, including module count, capacity, and rated data rate. A kit's presence on the QVL confirms testing only in the listed configuration and does not guarantee the same result with every CPU sample, another BIOS version, or mixed kits. At the same time, the absence of a particular kit from the QVL does not by itself indicate incompatibility: a motherboard manufacturer cannot physically test every memory kit available.

WHY XMP LOOKS DIFFERENT ON TWO MOTHERBOARDS

The SPD does not store absolutely every secondary and tertiary timing. The BIOS calculates some values itself and obtains others during memory training. The same XMP can therefore produce different Auto timings on different motherboards or after a BIOS update. XMP is a starting recipe, not a complete snapshot of every system register.

THREE LAYERS OF A SINGLE PROFILE

The PMIC (Power Management Integrated Circuit) converts motherboard power into the DRAM supply rails: VDD, VDDQ and VPP. It sets their voltages, manages startup and monitors overloads and overheating. The PMIC is one chip; the complete power circuit also includes inductors, capacitors and other components on the module PCB.

Desktop DDR5 solutions include Richtek RTQ5132/RTQ5136, Renesas P8911 and ANPEC APW8502C. As of 11 October 2026, newer confirmed client designs include the second-generation Renesas RRG5332, a JEDEC PMIC5120-class device, and Think Future SY5889 with CUDIMM support. Model names and JEDEC classes describe the product and its capabilities; silicon revisions require separate identification. The table lists models or literal package markings checked against teardown photographs.

For overclocking, check the available voltage range, module configuration, BIOS support and power stability under load. Richtek RTQ5136 and Think Future SY5888 offer an extended VDD/VDDQ range up to 2.2 V; SY5888 also specifies Intel XMP 3.0 OC support. Access to higher voltages depends on the module and motherboard. A High DRAM Voltage switch in the BIOS cannot remove every restriction. Check physical markings when identifying the PMIC: SPD and BIOS identification can be wrong.

PMICS FOUND IN REVIEWED KITS

These are the reviewed samples; PMICs may differ between production batches of the same SKU.

A "32 GB" label indicates only total capacity. It does not show the number of ranks, device width, or density of a single die. These characteristics are independent and are often more important for overclocking than capacity itself.

HOW A TYPICAL DDR5 1Rx8 UDIMM IS ORGANIZED

RANK IS NOT A PCB SIDE

A rank is a logical layer of memory accessible through Chip Select. Each 32-bit DDR5 subchannel selects its own group of DRAM devices; together, the two groups form a 64-bit module rank. 1Rx8 means one such layer built with x8 devices; 2Rx8 means two. The number of PCB sides is not a reliable indicator: check the SPD, markings, and datasheet.

x8 AND x16 ARE THE WIDTH OF ONE DRAM DEVICE

A 64-bit non-ECC rank requires eight x8 devices or four x16 devices. On one 32-bit subchannel, that means four x8 devices or two x16 devices. x16 reduces the number of packages, but usually provides fewer internal bank groups and less parallelism. High-performance desktop kits more often use x8.

A dual-rank DIMM still has two physical subchannels; each one simply has two ranks available. This is sometimes called "four subchannels," but it merely refers to four rank x subchannel combinations, not four separately wired channels.

DIE DENSITY DETERMINES RANK CAPACITY

WHAT IS CALLED NON-BINARY DDR5

Non-binary DDR5 refers to memory built with 24-Gbit dies, typically in 24 GB and 48 GB capacities. In a standard non-ECC DIMM using x8 SDP devices, one package contains one die. Capacity in GB = density of one die in Gbit x number of dies per rank x number of ranks / 8.

HOW TO CHECK YOUR MODULE'S ORGANIZATION

Memory-controller load depends on DIMMs and ranks per channel, x8/x16 organization, die density, motherboard routing, frequency and timings. The same total capacity can therefore impose a very different electrical load.

TYPICAL KITS FROM 2024-2026

SAME NUMBER OF RANKS, DIFFERENT ELECTRICAL TOPOLOGY

WHAT REDUCES FREQUENCY HEADROOM THE MOST

A second DIMM on a channel is usually a heavier load than a second rank within one module: it engages the second routing branch and adds the electrical load of another module. Four DIMMs therefore tend to require a lower frequency than two, even with the same total number of ranks. A true 1SPC motherboard with one slot per channel also differs from a four-slot 2SPC motherboard, where the empty second branch still physically exists.

At the same MT/s, 2R may slightly improve performance through rank interleaving: while one rank is busy with an internal operation, the IMC accesses the other. In extreme overclocking, this benefit is often outweighed by the lower achievable frequency.

OFFICIAL INTEL MODES SHOW THE EFFECT OF LOAD

A new memory generation changes more than speed. The electrical interface, operating voltage, pinout, key position, and internal DIMM organization change with it. Similar appearance does not imply compatibility, and with DDR5 the physical IC layout must be distinguished from logical rank organization.

THREE GENERATIONS - THREE INCOMPATIBLE SLOTS

DDR3L uses 1.35 V. DDR4 and DDR5 both have 288 pins, but differ in pinout and key position.

WHAT IS FOUND ON A TYPICAL DDR5 1Rx8 UDIMM

TeamGroup T-Force Xtreem DDR5-8200, 24 GB: 1Rx8, eight SK hynix 24-Gbit x8 DRAM ICs.

PCB SIDES AND RANK ARE UNRELATED

Rank organization and the placement of ICs on PCB sides are different characteristics. Single Rank (1R) means one logical rank selected by one group of Chip Select signals. Double-sided (DS) means only that ICs are physically soldered to both sides of the PCB. These characteristics coincided on many DDR3/DDR4 modules, which perpetuated the confusion.

In theory, rank is unrelated to PCB side: rank organization and IC placement are different characteristics. However, among standard DDR5 UDIMMs/SO-DIMMs actually in production, I found no confirmed 2R + SS module. Every verified 2Rx8 DDR5 module uses 16 DRAM packages and is DS.

On mainstream desktop DDR5 UDIMMs, 2R is usually built from 16 separate x8 SDPs (Single-Die Packages), resulting in 8 packages on the front and 8 on the back. For example, Kingston describes current 64 GB DDR5 UDIMMs built with 32-Gbit DRAM as exactly 16 x x8 = 64 GB, 2 ranks.

NON-ECC DDR5 UDIMM EXAMPLES

The SO-DIMM example is Kingston KVR56S46BD8-32: 16 FBGAs, 8 on each side. [9]

TYPICAL NON-ECC DDR5 x8 UDIMM USING SDPs

DRAM stands for Dynamic Random Access Memory. On a memory module, it takes the form of ICs (Integrated Circuits). A single package may contain one or more dies.

ONE PACKAGE, DIFFERENT DIE COUNTS

Examples of wire-bonded packages

SDP · one die

Single-Die Package

DDP · two dies

Dual-Die Package

• 1 Molding compound
• 2 Silicon die
• 3 Bond wires
• 4 Package substrate
• 5 Solder balls
• 6 Adhesive layer

FBGA (Fine-Pitch Ball Grid Array) is a package with closely spaced solder balls. The balls on its underside are soldered to the module PCB.

HOW TWO DIES FIT INTO ONE PACKAGE

DDP assembly variants · Invensas

1. Center pads

Both dies face up. Bond wires connect the center pads to the substrate.

2. Edge pads

RDL routes the pads to the edges. A spacer separates the dies.

3. Back-to-back

The lower die connects through a window in the substrate; the upper die connects from above.

4. Both dies face down

The dies are offset. Bond wires pass through windows in the substrate.

RDL (Redistribution Layer) relocates the pads across the die surface.

DRAM die density (also called DRAM IC density) is the amount of data stored by one die. It is specified in gigabits, such as 16, 24 or 32 Gbit. The brand on the heat spreader identifies the kit manufacturer, but the DRAM dies themselves may have been made by SK hynix, Samsung, or Micron, for example. An exact description requires four fields: manufacturer, DDR generation, density, and revision.

CORRECT NOTATION

OVERCLOCKING SHORTHAND

HOW TO READ THE PART NUMBER INSTEAD OF GUESSING FROM XMP

A full SK hynix code such as H5CGD8M... can be read by field: H5C indicates DDR5, GD indicates 24-Gbit density, 8 indicates x8 organization, and M indicates the die generation; the remaining suffix encodes other product parameters. Micron places the revision after a colon: for example, 16-Gbit :D and 24-Gbit :B are different products. Samsung must be tied to the full K4R... part number because the letter B appears in both DDR4 and DDR5.

The most reliable sources are the module's official datasheet and the full number printed on the DRAM IC. The SPD and utilities help, but if the exact revision cannot be determined, label it accordingly as an assumption. XMP frequency, voltage, and capacity alone do not prove the die type: the kit manufacturer may change ICs without changing the marketing name.

DIE REVISION AND PROCESS NODE ARE NOT THE SAME THING

A-die, B-die, and M-die describe a revision or design generation within a manufacturer's naming scheme. 1anm, 1bnm, 1alpha, and 1beta name a process node. The letter is not an official quality grade and does not promise specific MT/s, tCL, or a permissible voltage.

HOW TO CONFIRM THE IC TYPE

Manufacturers can use the same ICs in kits with different XMP profiles, PCBs, PMICs and voltages. The revision describes the die design; binning establishes the kit's validated operating point.

Binning, or screening, is the sorting of ICs and assembled modules by their ability to operate at a specified point: particular MT/s, timings, and voltage. The manufacturer validates the result and sells it as a separate SKU with a specific XMP profile.

HOW AN XMP KIT IS CREATED

HOW TO COMPARE KIT BINNING

The same H16A or H24M ICs appear in kits with different profiles. One kit is selected for frequency, another for low tCL, lower voltage or capacity. Compare them for the same task and with matching module organization.

ONE DATA RATE — DIFFERENT OPERATING POINTS

* 7200 MT/s is the established practical stable community target for 2 × 32 and 2 × 48 GB.

[1] G.SKILL F5-6000J2836F24GX2-TZ5NRW

[2] G.SKILL F5-6000J3036F48GX2-TR5S

[3] G.SKILL F5-6000J3244G64GX2-TZ5NR

WHAT A LOWER PROFILE VOLTAGE TELLS YOU

With matching ICs, density, capacity, rank, PCB, frequency and timings, lower VDD/VDDQ suggests the kit needs less voltage at that operating point. The manufacturer specifies a validated voltage; testing establishes the minimum working value and OC headroom. The IMC, motherboard and cooling also affect the result. Kits are validated as a set, so mixed kits require fresh testing.

Desktop LGA1700 and LGA1851 platforms have two memory channels: A and B. First count the slots on the board, then the modules installed in each channel.

2-DIMM / 4-DIMM board describes its slot count. 2 × 24 GB means two 24 GB modules.

1R / 2R means one or two ranks in a DIMM. 1DPC 2R means one dual-rank DIMM per channel.

WHAT THIS LOOKS LIKE ON A BOARD

1SPC + 1DPC

2 slots, 2 modules. One each in A and B. There is no room for four DIMMs.

2SPC + 1DPC

4 slots, 2 modules. A2 and B2 are populated; A1 and B1 are empty. The board remains 2SPC.

2SPC + 2DPC

4 slots, 4 modules. A1, A2, B1, and B2 are populated. Two DIMMs per channel.

HOW SLOTS IN ONE CHANNEL ARE CONNECTED

Daisy Chain and T-topology allow 1DPC and 2DPC. Population does not change the board's routing.

1SPC · one slot

One connector on the path. No second slot or branches to it.

2SPC · Daisy Chain

The line passes through the A1 and A2 connection points in sequence.

2SPC · T-topology

Branches of similar electrical length run from a common point to the slots.

With three DIMMs, A and B have different populations. A/B are the platform’s two channels; DDR5’s 32-bit subchannels do not change this classification.

Z790 alone does not make a motherboard faster than Z690. For memory, physical 1SPC routing, PCB quality, BIOS/MRC, and recovery features matter more. The selections below include 2-DIMM models, standard 4-DIMM Z790 boards, and expensive E-ATX flagships. Overall, 2-DIMM motherboards provide better memory training than the rest.

2-DIMM / TRUE 1SPC: MOTHERBOARDS FOR MAXIMUM FREQUENCY

* 64 GB according to the original EVGA specification; 96 GB confirmed by later 2 x 48 GB kits.

4-DIMM / 2SPC: CURRENT Z790 MOTHERBOARDS FOR DAILY USE AND CAPACITY

4-DIMM / 2SPC: E-ATX FLAGSHIPS FOR CAPACITY AND FEATURES

OC speed and capacity maxima are separate; the operating point depends on the CPU, BIOS and kit. GAMING X AX lists 7600 for 13th/14th-gen Core i7/i9. All three MSI QVLs for 14 Gen K list Kingston KF556C40BWAK4-128: 4 × 32 GB at 5600. * The five ASUS boards above support 256 GB with updated BIOS; their specifications still list 192 GB.

The main memory-related change in LGA1851 is official CUDIMM support. A Clocked Unbuffered DIMM remains a conventional unbuffered module for data and commands, but adds a separate Clock Driver, or CKD. It receives the clock signal, cleans it up, and reshapes it before sending it to the DRAM ICs.

WHAT EXACTLY THE CKD DOES

UDIMM AND CUDIMM ON CORE ULTRA 200S

PRACTICAL Z890 SELECTION: OC, STANDARD 4-DIMM, AND FLAGSHIPS

CKD BYPASS AND INTEL 200S BOOST

Both UDIMM and CUDIMM work on Z890. On some LGA1700 motherboards, CUDIMM is possible only through a BIOS-supported CKD bypass mode: the clock driver is bypassed, the CUDIMM advantages disappear, and frequency is limited by the older platform. Buying CUDIMM to accelerate LGA1700 is pointless. Intel 200S Boost is a separate official OC profile, while 200S Plus refers to updated CPU models. Boost specifies memory up to DDR5-8000, NGU/D2D up to 3.2 GHz, VccSA/VDD2 up to 1.20/1.40 V, and DRAM VDD/VDDQ up to 1.40 V with one DIMM installed per channel.

Maxsun appeals to enthusiasts as a relatively budget-friendly overclocking option: two memory slots and decent features for the money. The BIOS still leaves room for improvement, especially with manual timings, as the reviews below show.

PCB: printed circuit board; n/a: unconfirmed; OC: overclocking; data rates in MT/s. VRM layouts follow manufacturer/teardown data. An SPS current rating does not specify the current capability of the whole board.

* Z690ITX: RAA229131 in the product listing, RAA229132 in the teardown. ** Not all nine stages supply Vcore. *** Low-loss PCB material and back-drilling (removal of unused plated via stubs).

Z790ITX WIFI: a budget option for LGA1700

Tom’s Hardware (2023): i9-13900K, BIOS H5.3G, TeamGroup XMP-7200 worked without issues. i2HARD (2023) reached 7200 with an i9-13900KF, H4.2G and 2×16 GB Patriot 5600, but CL rose to 58 because manual timings were applied incorrectly. H7.4G included timing optimizations. The early review does not tell us how newer firmware behaves. I would consider it for a sensible 7200 target, rather than buy it for the advertised 8200.

Z890 VERTEX: the main candidate for high data rates

Overclocking.com (2025) used an Ultra 7 265K and 2×24 GB G.Skill with Hynix M. Results: 8800 CL36 with ambient memory cooling and extreme CPU cooling; 9400 CL36 at roughly -70 °C on the memory in y-cruncher 2.5B; 9494 CL36 in 7-Zip. 11200 was a separate bench. There is potential, but the daily-use ceiling remains unproven; the reviewer missed Safe Boot/Retry for quick recovery after a failed boot.

NEWLY SHOWN BOARDS: KEEP THESE SEPARATE FOR NOW

Choose by test results and BIOS behavior. Two slots and good routing help overclocking; the achieved frequency also depends on the IMC and kit and requires stability testing.

SPC means slots per channel. Population lists supported DPC configurations, rather than an installed kit.

Channels A/B follow the board manual; DDR5 subchannels are not counted separately here.

Board names link to specifications; confirmed topology labels link to their sources.

Point-to-point means the controller connects to the sole socket in a channel: a structural classification based on board documentation.

* GIGABYTE calls the Z690/Z790 Tachyon layout “2-DIMM daisy chain”; this table classifies them as Point-to-point by the number of sockets in each channel.

The right choice starts not with the highest XMP profile, but with the required capacity. Capacity determines module and rank count, which in turn determines the appropriate motherboard topology. Only then does it make sense to choose a CPU, specific IC, and realistic frequency target.

DECISION ORDER

TYPICAL SCENARIOS

PROCESSOR

For full manual control, choose an unlocked K/KF processor and a Z-series motherboard. The individual IMC sample remains a lottery: a more expensive CPU model does not promise a stronger controller. On LGA1851, Intel 200S Boost also requires a suitable K/KF processor, motherboard, and BIOS.

MOTHERBOARD

For maximum frequency with two modules, choose a true 1SPC OC motherboard. For high capacity and flexibility, choose four slots while accepting a lower ceiling when fully populated. The Z790 Apex Encore is officially limited to 96 GB. Yet BIOS 0904, dated February 16, 2024, promises “Enhanced compatibility with 256GB memory.” I think the developers were high when they wrote that: this note does not override the specification limit. So 128-192 GB on LGA1700 requires another motherboard. Check the exact QVL, current BIOS, support for the required density and CUDIMM, recovery features, and DIMM airflow rather than a general marketing claim.

MEMORY KIT

Buy one matched kit with the final capacity you need. Check the part number, number of DIMMs, rank, die density, XMP voltage, and presence of a temperature sensor. Intel does not officially specify more than 192 GB for LGA1700 even if an individual motherboard lists 256 GB support; for LGA1851, the current Core Ultra 200S ARK already specifies up to 256 GB. In practice, the final limit is determined by the combination of CPU, motherboard, BIOS version, and specific memory kit.