Voltages

DDR5 overclocking depends not on one voltage, but on a chain of several independent domains. Some are inside the processor, some belong to the channel's electrical interface, while VDD, VDDQ, and VPP are generated by the PMIC on the module itself. First separate these areas physically; only then look for a relationship with the error.

HOW TO READ THE NUMBER SHOWN BY THE BIOS

VCCSA powers the System Agent, a broader domain than the memory controller alone. SA therefore affects the overall memory and uncore operating point as well as MRC repeatability, but is neither a DRAM voltage nor a substitute for separate VDD2. On Z890, SA remains part of the overall uncore/NGU operating point, but does not directly power D2D: D2D has separate domains and ratios.

Insufficient SA may appear as POST loops, poor cold boot, or inconsistent training results. Too much can cause the same symptoms: noise, reference levels, and the PHY range found by training all change. Find a repeatable range in small steps, not the highest possible number.

On ASUS Z790, the IVR Transmitter VDDQ Voltage entry literally sets the internal transmitter voltage of the memory controller. This is part of the CPU-side channel: it participates in shaping DQ/DQS edges, write training, Vref/ODT, and electrical margin at high speed.

On Z890, the separate IVR Transmitter VDDQ name is gone. Advanced Memory Voltages adds VccDdqControl Bypass and Vddq Voltage Override, alongside VccIog and VccClk fields. The public ASUS manual confirms these low-level CPU/PHY-side settings, but does not disclose their exact electrical mapping. Vddq Override is functionally similar to the former TX domain, but cannot be treated as a 1:1 rename or assigned a copied Z790 value.

ASUS calls this rail Memory Controller Voltage on both Z790 and Z890. Its hardware name in Intel documentation is VDD2: power for the memory-controller interface and processor DDR I/O. HWiNFO usually shows it as IMC VDD. It is neither the module's VDD nor TX VDDQ.

DRAM VDD and DRAM VDDQ reside on the module itself and are generated by its PMIC. VDD powers the DRAM core, while VDDQ powers the IC data I/O. The nominal DDR5 starting point is 1.10/1.10 V; XMP almost always raises both rails because it overclocks frequency and timings simultaneously.

HOW VOLTAGES RELATE TO FREQUENCY AND TIMINGS

Every voltage has an operating range. Below it, electrical margin is insufficient; above it, edge rate, Vref, ODT, noise, and heat change, and after full retraining the operating range may narrow again. The dynamic component of power scales roughly as Pdyn ~ C x V^2 x f, so a small increase in V at high frequency noticeably affects heat.

My Z790 Apex Encore / BIOS 2202 / 2 x 24 GB / DDR5-8200 profile uses SA 1.22; TX 1.35; MC 1.40; VDD 1.49; VDDQ 1.44 V. Telemetry shows similar but unequal numbers. This illustrates the difference between setpoints and sensor readings; it is not a ready-made profile or safe range.

The ranges below are very approximate guidelines based on my personal opinion. There is no single official safe range for manual overclocking: platform, IC type and density, rank count, number of modules, and other factors all matter.

VOLTAGE RANGES, V

Official Z890 reference: Intel 200S Boost - SA ≤1.20 V.

1 A-die, non-binary M-die; 2 air; 3 water; 4 reduce only while retaining stability, down to 1.10–1.15 V; 5 in my observations within the community, sustained TX VDDQ >1.45 V coincided with cases of failed 13900K and 14900K processors. These are observations, not a confirmed failure threshold.

DRAM VDD AND VDDQ: TUNED SEPARATELY

VDD powers DRAM circuitry; VDDQ powers I/O. The rail-to-rail voltage difference is limited by IC/PMIC specifications; maximum ratings are not operating conditions. No safe OC delta has been established. Fix VDD, frequency, and timings, then lower VDDQ in 10-20 mV steps. After warm-up and several complete training cycles, find the lower passing boundary, then select a value with a small margin inside the repeatable range. Passing tests does not prove that an overclock is safe.

A MEMORY WATER BLOCK: GOOD THERMAL HEADROOM

With good contact and cool liquid, a water block reduces DIMM temperature and provides headroom for timings, frequency, or lower voltage. If the limit is already the IMC or signal quality, there may be no gain.

Comparison of the same 2 x 24 GB M-die pair: for 8200 CL34, a 140 mm fan at 800 rpm required 1.56 V at 49.2/48.5 °C; the water block required 1.50 V at 31.2/31.0 °C. This was AM5, voltages were tuned separately, and validation was 1 hour of Karhu plus about 25 minutes of TM5. Temperature was read from the SPD Hub; I did not study service life. The example is provided for comparison.

LOW TEMPERATURE DOES NOT ELIMINATE ELECTRICAL STRESS

TI, SSZY028 (2017), Fig. 5. High-voltage insulators. The voltages and service lives shown do not apply to DDR5. The figure illustrates the principle.

Higher voltage increases the electric field in the dielectric. Prolonged exposure gradually degrades its insulating properties and may end in breakdown: TDDB. Heat accelerates several aging mechanisms.

A water block reduces temperature, not the electric field from the configured VDD/VDDQ. A cold module can therefore pass tests while still losing service life. Lower temperature reduces the thermal component of risk; it does not make high voltage safe.

In the TI graph, the X-axis is voltage and the Y-axis is time to breakdown on a logarithmic scale. The higher the test voltage, the shorter the time. The points represent failure of 63% of samples; the dashed line predicts a 1 ppm failure rate.