INTEL GUIDE FOR LGA1700 / LGA1851PDF · pages 13–16Pages 13–16

Tuning and Validation

5.1 AC Load-Line Tuning Procedure

PDF · 13Page 13

Change one significant parameter at a time. First establish a reproducible baseline, then find a stable AC value while keeping LLC, DC, frequency policy, and limits unchanged. Memory must already be validated; otherwise, errors cannot be confidently linked to the latest CPU change.

The goal of AC undervolting is the lowest reasonable AC, not the absolute minimum or an undervolt pushed to the floor: balance lower voltage, power consumption, and temperature with full baseline performance, correct computation, and no unwanted CEP intervention. An excessively low AC may produce no WHEA events, BSODs, or crashes, yet CEP may already be reducing Effective Clocks through clock stretching and reducing performance. The absence of WHEA does not prove that the undervolt is optimal.

  1. Record the baseline

    Save the profile, BIOS/microcode version, HT, memory settings, limits, temperatures, and results of the selected tests. For a new system, first validate the recommended Intel configuration.

  2. Choose operating limits

    PL1/PL2, ICCMAX, and the temperature ceiling must suit the cooling. Do not change them while tuning AC.

  3. Choose a moderate LLC

    In my example, this is Level 5. The matching DC values for ASUS are given in 3.2; the entire profile does not transfer automatically. Do not chase minimum Vdroop just for a good-looking graph.

  4. Separate AC and DC

    For manual tuning, disable Synch ACDC. Set DC using Table 3.2 and verify AC/DC after boot. Do not use DC to lower reported power.

  5. Validate the initial AC

    In this method, after selecting LLC and verifying the applied DC value, setting AC = DC is recommended as a reproducible starting point, not a universal optimum or a value guaranteed to be minimal, safe, or a target. Before lowering AC, validate and record the baseline: test result, Effective Clocks, VOUT/voltage, and the absence of computational errors and signs of CEP intervention. Then lower only AC; DC remains tied to LLC.

  6. Lower AC and compare results

    Lower the AC value itself by 0.02-0.05 mΩ per iteration. If errors or reproducible performance loss appear, return to the previous validated value and refine the boundary with smaller steps of 0.01-0.02 mΩ. These numbers are step sizes, not target AC values. Check errors, WHEA, the test result, and Effective Clocks.

    In the original example, AC started at 0.40 mΩ and was then reduced to 0.35-0.30 mΩ. These values illustrate one specific configuration; they do not define a mandatory starting point or a universal lower boundary.

  7. Separate the load types

    Test heavy multithreaded operation separately from single-threaded or lightly threaded high boost and load/idle transitions. Lowering AC does not guarantee a solution to a problem at the upper V/F point.

  8. Back away from the boundary and repeat

    If an error or performance loss occurs, undo the last step. Keep the final AC above the boundary you found, with a margin confirmed by repeated testing in warm conditions.

DOCUMENTATION CONSULTED: ASUS BIOS guides and information; Intel specifications and explanations. ASUS ROG Z790 BIOS Manual, Intel Vmin Update, Intel UVP, Intel CEP 13

5.2 Monitoring and the Reference Operating Point

PDF · 14Page 14
Monitoring and the Reference Operating Point
Sensor / metricHow to use it
Core VIDsThe collapsed row averages core VIDs, not their maximum or measured Vcore. Expand the group; compare the same interval (9.3.1).
VRM Vcore Voltage (VOUT)Assess the output voltage of the corresponding VRM when a reliable telemetry channel is available.
Vcore / Die SenseCompare with VOUT on this board. Account separately for differences in measurement points, accuracy, and polling.
VRM Vcore Current (IOUT)Assess rail current and its relationship to the load. Slow sampling does not capture every fast peak.
CPU Package / IA PowerMonitor the effect of PL and the consistency of the model. Package power and a single VRM rail do not have to match to the watt.
Core Effective ClocksAveraged clock speed accounting for core activity and sleep. Compare with the test result under a sustained, comparable load.
Limit Reasons / WHEALimit reasons and hardware errors. The absence of WHEA does not rule out CEP activation or a computational error.
CPU / VRM temperaturesRecord current and maximum values, cooling conditions, and throttling flags.

y-cruncher screenshot: distinguish Current from Maximum

Monitoring and the Reference Operating Point
MetricCurrent in the screenshotMaximum over the interval
Core VIDs (aggregate)1.278 V1.472 V
Vcore / VRM VOUT1.288 / 1.288 V1.430 / 1.409 V
VRM IOUT244 A259 A
CPU Package Power313.696 W318.643 W
Core Max75 °C94 °C (summer)
VR VCC Temperature53 °C54 °C

1.288 V × 244 A ≈ 314.3 W is close to the current Package reading of 313.7 W, but does not prove DC calibration. These are different channels, and their sampling is not guaranteed to be synchronized in hardware. Maxima in different rows may have occurred at different times.

DOCUMENTATION CONSULTED: explanations by the HWiNFO author; Intel specifications and explanations; material from the working example. HWiNFO: VID and DC Load-line, HWiNFO: Effective Clock, Intel VCCCORE, Author's Screenshots 14

5.3 Stability Testing and Diagnostics

PDF · 15Page 15

Time alone does not guarantee stability. Record the actual P/E/Ring, workload and limit reasons: passing under limits does not validate the upper ratios. Compare small gains with variation across several baseline runs.

Stability Testing and Diagnostics
Test scenarioWhat to checkCondition for proceeding
5-10 min after an AC stepReproducible load and result, errors, and temperaturesNo new errors or unexplained performance loss
y-cruncher SVT + VT320-30 min: quick screening; 45-60 min: candidate; then longer tests of the required modesBoth tests complete without errors; limit flags are understood
OCCT / changing loadsVariable data sets and core cycling; separately, reproducible load/idle transitionsNo errors, reboots, or performance loss
Per-core / small thread countsEvery P-core, including preferred cores; upper clock speeds under suitable conditionsNo errors at clock speeds actually reachable in this mode
Idle, sleep/wake, cold bootPower-state transitions and repeatable startup behaviorNo hangs, occasional app crashes, or new WHEA events
Real workloads and a warm roomCombined load, noise, heat, and expected performanceThe profile meets the stated daily-use scenario

Quick diagnostics

Stability Testing and Diagnostics
ObservationDo not jump to conclusionsNext step
SVT / VT3 errorThis is not a definitive test of the cores alone: Ring, IMC, DRAM, and power delivery may be involvedWith validated memory unchanged, undo the last AC step and repeat
Error only at high boostHeavy all-core testing did not validate this modeCheck the specific cores and bins; do not use DC as a fix
Low Effective ClockThis is normal at idle; under load, it can have different causesCompare the result, core activity, and limit reasons
Failure when the load is removedSoftware has not proven that overshoot was the causeRepeat transitions and restore the baseline; after changing LLC, recheck AC/DC
Unexpected change in Package PowerThe DC model, limits, or a different frequency mode may be involvedCheck the applied settings and repeat the same load
DOCUMENTATION CONSULTED: software and Windows documentation; explanations by the HWiNFO author. y-cruncher Version History, OCCT CPU, OCCT CPU + RAM, HWiNFO: Effective Clock, Microsoft WHEA 15

5.4 y-cruncher: Component Stress Tests

PDF · 16Page 16

Use Component Stress Tester, not the π benchmark. The screenshot shows the Windows 0.8.7.9547b menu, not a new CPU test. I record the version, binary, threads and memory: the instruction set depends on the binary; AVX2 describes this run. Mem/Thread is memory per thread and varies by component.

y-cruncher Component Stress Tester settings

First select the required components; then choose 0 - Start Stress-Testing.

WHAT EACH COMPONENT DOES

y-cruncher: Component Stress Tests
TagAlgorithmPrimary loadRole in CPU undervolting
BKTBasecase + Karatsuba*Scalar integer multiplication; small working setAdditional arithmetic coverage for the CPU
BBPBBP Digit ExtractionVector floating-point arithmetic, small working setCPU computation; not a check of all allocated RAM
SFTv4Small In-Cache FFTv4Floating-point arithmetic; an in-cache fast Fourier transform (FFT)CPU/cache and cooling; similar in focus to OCCT CPU
SNTSmall In-Cache N63An in-cache integer number-theoretic transform (NTT)Tests CPU/cache with a different type of math
SVTSmall In-Cache VT3Small VT3: in-cache vector computationChecks CPU/cache alongside the large VT3 test
FFTv4Fast Fourier Transform v4FFT with a large working set; dependent on RAM bandwidthMixed CPU/cache/IMC/RAM load
N63Classic 64-bit NTT v264-bit integer NTT; large working setAn independent combined CPU and RAM load
VT3Vector-Scalable Transform v3Vector transform; large working set, CPU + IMC + RAMTests the profile under a mixed load; replacement for legacy VST

* The BKT name in Command Lines.txt includes Toom-Cook; the developer states that Toom-3 was removed.

DOCUMENTATION CONSULTED: software and Windows documentation. y-cruncher: Official Release, y-cruncher Version History, y-cruncher FAQ, y-cruncher: Memory Allocation 16