Tuning and Validation
5.1 AC Load-Line Tuning Procedure
PDF · 13Page 13Change one significant parameter at a time. First establish a reproducible baseline, then find a stable AC value while keeping LLC, DC, frequency policy, and limits unchanged. Memory must already be validated; otherwise, errors cannot be confidently linked to the latest CPU change.
The goal of AC undervolting is the lowest reasonable AC, not the absolute minimum or an undervolt pushed to the floor: balance lower voltage, power consumption, and temperature with full baseline performance, correct computation, and no unwanted CEP intervention. An excessively low AC may produce no WHEA events, BSODs, or crashes, yet CEP may already be reducing Effective Clocks through clock stretching and reducing performance. The absence of WHEA does not prove that the undervolt is optimal.
Record the baseline
Save the profile, BIOS/microcode version, HT, memory settings, limits, temperatures, and results of the selected tests. For a new system, first validate the recommended Intel configuration.
Choose operating limits
PL1/PL2, ICCMAX, and the temperature ceiling must suit the cooling. Do not change them while tuning AC.
Choose a moderate LLC
In my example, this is Level 5. The matching DC values for ASUS are given in 3.2; the entire profile does not transfer automatically. Do not chase minimum Vdroop just for a good-looking graph.
Separate AC and DC
For manual tuning, disable Synch ACDC. Set DC using Table 3.2 and verify AC/DC after boot. Do not use DC to lower reported power.
Validate the initial AC
In this method, after selecting LLC and verifying the applied DC value, setting AC = DC is recommended as a reproducible starting point, not a universal optimum or a value guaranteed to be minimal, safe, or a target. Before lowering AC, validate and record the baseline: test result, Effective Clocks, VOUT/voltage, and the absence of computational errors and signs of CEP intervention. Then lower only AC; DC remains tied to LLC.
Lower AC and compare results
Lower the AC value itself by 0.02-0.05 mΩ per iteration. If errors or reproducible performance loss appear, return to the previous validated value and refine the boundary with smaller steps of 0.01-0.02 mΩ. These numbers are step sizes, not target AC values. Check errors, WHEA, the test result, and Effective Clocks.
In the original example, AC started at 0.40 mΩ and was then reduced to 0.35-0.30 mΩ. These values illustrate one specific configuration; they do not define a mandatory starting point or a universal lower boundary.
Separate the load types
Test heavy multithreaded operation separately from single-threaded or lightly threaded high boost and load/idle transitions. Lowering AC does not guarantee a solution to a problem at the upper V/F point.
Back away from the boundary and repeat
If an error or performance loss occurs, undo the last step. Keep the final AC above the boundary you found, with a margin confirmed by repeated testing in warm conditions.
5.2 Monitoring and the Reference Operating Point
PDF · 14Page 14| Sensor / metric | How to use it |
|---|---|
| Core VIDs | The collapsed row averages core VIDs, not their maximum or measured Vcore. Expand the group; compare the same interval (9.3.1). |
| VRM Vcore Voltage (VOUT) | Assess the output voltage of the corresponding VRM when a reliable telemetry channel is available. |
| Vcore / Die Sense | Compare with VOUT on this board. Account separately for differences in measurement points, accuracy, and polling. |
| VRM Vcore Current (IOUT) | Assess rail current and its relationship to the load. Slow sampling does not capture every fast peak. |
| CPU Package / IA Power | Monitor the effect of PL and the consistency of the model. Package power and a single VRM rail do not have to match to the watt. |
| Core Effective Clocks | Averaged clock speed accounting for core activity and sleep. Compare with the test result under a sustained, comparable load. |
| Limit Reasons / WHEA | Limit reasons and hardware errors. The absence of WHEA does not rule out CEP activation or a computational error. |
| CPU / VRM temperatures | Record current and maximum values, cooling conditions, and throttling flags. |
y-cruncher screenshot: distinguish Current from Maximum
| Metric | Current in the screenshot | Maximum over the interval |
|---|---|---|
| Core VIDs (aggregate) | 1.278 V | 1.472 V |
| Vcore / VRM VOUT | 1.288 / 1.288 V | 1.430 / 1.409 V |
| VRM IOUT | 244 A | 259 A |
| CPU Package Power | 313.696 W | 318.643 W |
| Core Max | 75 °C | 94 °C (summer) |
| VR VCC Temperature | 53 °C | 54 °C |
1.288 V × 244 A ≈ 314.3 W is close to the current Package reading of 313.7 W, but does not prove DC calibration. These are different channels, and their sampling is not guaranteed to be synchronized in hardware. Maxima in different rows may have occurred at different times.
5.3 Stability Testing and Diagnostics
PDF · 15Page 15Time alone does not guarantee stability. Record the actual P/E/Ring, workload and limit reasons: passing under limits does not validate the upper ratios. Compare small gains with variation across several baseline runs.
| Test scenario | What to check | Condition for proceeding |
|---|---|---|
| 5-10 min after an AC step | Reproducible load and result, errors, and temperatures | No new errors or unexplained performance loss |
| y-cruncher SVT + VT3 | 20-30 min: quick screening; 45-60 min: candidate; then longer tests of the required modes | Both tests complete without errors; limit flags are understood |
| OCCT / changing loads | Variable data sets and core cycling; separately, reproducible load/idle transitions | No errors, reboots, or performance loss |
| Per-core / small thread counts | Every P-core, including preferred cores; upper clock speeds under suitable conditions | No errors at clock speeds actually reachable in this mode |
| Idle, sleep/wake, cold boot | Power-state transitions and repeatable startup behavior | No hangs, occasional app crashes, or new WHEA events |
| Real workloads and a warm room | Combined load, noise, heat, and expected performance | The profile meets the stated daily-use scenario |
Quick diagnostics
| Observation | Do not jump to conclusions | Next step |
|---|---|---|
| SVT / VT3 error | This is not a definitive test of the cores alone: Ring, IMC, DRAM, and power delivery may be involved | With validated memory unchanged, undo the last AC step and repeat |
| Error only at high boost | Heavy all-core testing did not validate this mode | Check the specific cores and bins; do not use DC as a fix |
| Low Effective Clock | This is normal at idle; under load, it can have different causes | Compare the result, core activity, and limit reasons |
| Failure when the load is removed | Software has not proven that overshoot was the cause | Repeat transitions and restore the baseline; after changing LLC, recheck AC/DC |
| Unexpected change in Package Power | The DC model, limits, or a different frequency mode may be involved | Check the applied settings and repeat the same load |
5.4 y-cruncher: Component Stress Tests
PDF · 16Page 16Use Component Stress Tester, not the π benchmark. The screenshot shows the Windows 0.8.7.9547b menu, not a new CPU test. I record the version, binary, threads and memory: the instruction set depends on the binary; AVX2 describes this run. Mem/Thread is memory per thread and varies by component.

First select the required components; then choose 0 - Start Stress-Testing.
WHAT EACH COMPONENT DOES
| Tag | Algorithm | Primary load | Role in CPU undervolting |
|---|---|---|---|
| BKT | Basecase + Karatsuba* | Scalar integer multiplication; small working set | Additional arithmetic coverage for the CPU |
| BBP | BBP Digit Extraction | Vector floating-point arithmetic, small working set | CPU computation; not a check of all allocated RAM |
| SFTv4 | Small In-Cache FFTv4 | Floating-point arithmetic; an in-cache fast Fourier transform (FFT) | CPU/cache and cooling; similar in focus to OCCT CPU |
| SNT | Small In-Cache N63 | An in-cache integer number-theoretic transform (NTT) | Tests CPU/cache with a different type of math |
| SVT | Small In-Cache VT3 | Small VT3: in-cache vector computation | Checks CPU/cache alongside the large VT3 test |
| FFTv4 | Fast Fourier Transform v4 | FFT with a large working set; dependent on RAM bandwidth | Mixed CPU/cache/IMC/RAM load |
| N63 | Classic 64-bit NTT v2 | 64-bit integer NTT; large working set | An independent combined CPU and RAM load |
| VT3 | Vector-Scalable Transform v3 | Vector transform; large working set, CPU + IMC + RAM | Tests the profile under a mixed load; replacement for legacy VST |
* The BKT name in Command Lines.txt includes Toom-Cook; the developer states that Toom-3 was removed.