Glossary
11.1 Voltage and Power Delivery
PDF · 29Page 29CPU requests, the VRM and sensors operate at different levels. Click a term to open the relevant discussion.
| Term | English name | Explanation |
|---|---|---|
| SVID | Serial Voltage Identification | The command and telemetry interface between the CPU and VRM, not a Vcore sensor. Distinguish it from CPU-reported Core VIDs and the ASUS SVID Behavior policy (9.1, 9.3). |
| VID / Core VID | Voltage Identification | The CPU reports VID; it is not measured Vcore or necessarily a direct SVID command. Collapsed Core VIDs averages the core group, not its maximum. Expand it for detail (9.3.1). |
| V/F | Voltage / Frequency | The voltage-frequency relationship underlying adaptive control. The final operating request also depends on load, temperature and active adjustments. |
| AC LL | IA AC Load Line | Load-dependent adjustment of the voltage request. The main method lowers AC; 9.1 chooses and holds it constant beforehand, then changes the global offset. Manual AC and offset are not mutually exclusive. |
| DC LL | IA DC Load Line | A parameter in the droop model used for voltage and power accounting. This method chooses DC by LLC from 3.2. It is not IOUT calibration or a separate undervolting control. |
| LLC / Vdroop | Load-line Calibration / Voltage Droop | LLC changes the VRM load-line; Vdroop is its steady-state, load-dependent voltage drop. Stronger LLC does not guarantee better stability during load transitions. |
| VRM / VCCCORE | Voltage Regulator Module / Core Power Rail | The VRM converts power for the processor; VCCCORE denotes the power rail discussed here. Its voltage, current and power cannot be equated with the entire CPU Package. |
| VOUT / Vcore | VRM Output Voltage / Core Voltage | VOUT is regulator telemetry; Vcore is a motherboard sensing channel, Die Sense in the example. Measurement points and polling differ; equality is not required. Compare within the same interval (9.3.1). |
| IOUT / POUT | VRM Output Current / Power | The regulator output current and power reported by telemetry. Checking P ≈ U × I requires simultaneous readings from the same domain without sensor saturation. |
| Package / IA Power | CPU Package / IA Cores Power | Power estimates for the processor package and IA domain. Their coverage differs; a separate VRM power rail does not have to match Package Power. |
| Current Reporting | CPU Current Reporting | Scales the reported current. The manual retains 100%; deliberately underreporting current does not reduce actual consumption and may compromise accurate power control. |
| CPU Input Voltage LLC | CPU Input Voltage Load-line Calibration | Adjusts the load-line characteristic of the separate auxiliary CPU Input rail. This is not VCCCORE rail LLC or a setting for the main VRM's 12 V input. |
| Adaptive | Adaptive Voltage | Dynamically controls the voltage request according to CPU operating conditions. Section 9.1 retains adaptive mode and sets a negative offset separately; this is not fixed Vcore. |
| SVID offset | Global Core SVID Voltage Offset | An adjustment to the request with a "+" or "-" sign; negative for undervolting (9.1). It is not equivalent to a VRM offset or AC LL and does not guarantee an identical shift in all physical voltages. |
| FIXED | Manual VRM Voltage / Voltage Override | In 9.2, a manual Actual VRM Core Voltage target. It does not fix the clock frequency, eliminate Vdroop or prove the absence of power saving; verify actual behavior through measurements. |
| DLVR | Digital Linear Voltage Regulator | An additional voltage regulation stage in Arrow Lake. Its presence changes the interpretation of external VOUT and prevents direct transfer of Z790 electrical settings. |
| SVID Behavior | Auto / Trained | An ASUS policy. Auto depends on the BIOS; Trained uses a prediction for SVID settings. An advantage of Trained is not guaranteed. After changing it, check applied AC/DC values and load behavior (9.3). |
DOCUMENTATION CONSULTED: Intel specifications and explanations; ASUS BIOS guides and information; explanations by the HWiNFO author. Intel VCCCORE, ASUS ROG Z790 BIOS Manual, HWiNFO: VID and DC Load-line 29
11.2 Clocks, Limits and Protection
PDF · 30Page 30Terms for frequency policy, power and current limits, and protections. The saved BIOS value and the actual reason for limiting operation are checked separately. Click a term to open the relevant discussion.
| Term | English name | Explanation |
|---|---|---|
| P-core / E-core / HT | Performance Core / Efficient Core / Hyper-Threading | Performance P-cores and Efficient E-cores. HT provides two threads per P-core; it is off in the gaming profile, but can be enabled for the task with any method. Recheck Ring and CPU stability after a change. |
| Ratio / bin / Ring | Frequency Multiplier / Frequency Step / Ring Interconnect | Ratio is the frequency multiplier; bin is a frequency step. Ring is the interconnect and associated cache. Max. Cache Ratio sets a ceiling; Ring Down Bin allows reductions according to operating conditions. |
| ABT | Intel Adaptive Boost Technology | A mechanism for increasing multithreaded performance when operating conditions provide headroom. It is not the same as the maximum frequency of preferred cores with a small number of threads. |
| TBM 3.0 | Intel Turbo Boost Max Technology 3.0 | Uses preferred cores capable of higher frequencies. Their stability is checked with lightly threaded loads, which a heavy all-core test cannot replace. |
| TVB | Intel Thermal Velocity Boost | A temperature-dependent boost mechanism. TVB Voltage Optimizations adjusts the voltage request with temperature, while Enhanced TVB concerns the temperature conditions of the frequency policy. |
| PL1 / PL2 | Power Limit 1 / Power Limit 2 | Processor power limits. They set limits, not required power consumption; equal PL1 and PL2 do not specify a later transition to a lower limit. |
| Tau / Dual Tau Boost | Power Averaging Time Window / Dual Tau Boost | Tau relates to power averaging, not an exact PL2 timer. Dual Tau Boost is a separate Tau management policy, not a way to disable the current limit. |
| ICCMAX / Unlimited ICCMAX | Maximum Current Limit / Unlimited ICCMAX | ICCMAX is the CPU current limit. On ASUS Z790, Unlimited ICCMAX permits a range above 511.75 A; it does not disable all protections and is not VRM Current Capability. |
| CEP | Current Excursion Protection | A response to a voltage drop below an internal threshold: Effective Clocks and performance may decrease without errors. Disabled in 9.2.1 is a benchmark exception that removes this protection, not daily-use advice. |
| IA / SA | Intel Architecture / System Agent | Labels for different processor domains in settings and telemetry. For example, IA CEP and SA CEP apply to different domains rather than duplicating a single setting. |
| MCE | ASUS MultiCore Enhancement | ASUS policy for multithreaded operation. Disabled - Enforce All Limits enforces the specified limits, but manual values do not automatically become Intel Defaults. |
| Thermal limit / Throttling | Temperature Limit / Performance Throttling | A temperature threshold triggers thermal throttling, which reduces performance. Power, current, and other limits can also cause throttling. |
| C-states / Speed Shift | Processor Idle States / Intel Speed Shift Technology | C-states are idle states; Speed Shift / HWP provides hardware control of active P-states. Disabling HWP does not disable C-states or fix the frequency. |
| UVP | Undervolt Protection | Protection against software lowering voltage below the boot-time level. Disabling it is not a prerequisite for tuning voltage through BIOS. |
| EIST / HWP | Enhanced Intel SpeedStep / Hardware P-states | EIST manages operating states through the OS; HWP makes hardware selections within OS policy. They are disabled conditionally in 9.2.1: check whether Turbo depends on EIST. |
| Thermal Monitor / THRMTRIP | Thermal Monitor / Thermal Trip | Thermal Monitor reduces power to control CPU temperature; it is enabled in 9.2.1. THRMTRIP is an independent emergency shutdown, not a replacement for normal thermal protection. |
| C1E / Enhanced C-states | Enhanced C1 State | Enhanced C1. Author observation: Apex Encore / BIOS 2202 / ASUS Advanced OC Profile locks this field Enabled. CPU C-states is separate; the field does not prove idle-state entry (9.3). |
DOCUMENTATION CONSULTED: Intel specifications and explanations. Intel Datasheet, Intel CEP, Intel UVP, Intel Turbo Technologies 30
11.3 Measurement and Validation
PDF · 31Page 31Terms for reproducible tuning and validation. A successful test validates only the loads, clock speeds, and conditions actually tested, not every possible CPU workload. Click a term to open the relevant discussion.
| Term | English name | Explanation |
|---|---|---|
| Baseline | Reference Configuration | A saved starting configuration with known settings and results. AC, offset, or manual-voltage steps are compared against it; return to it if unexplained deterioration occurs. |
| Vmin | Minimum Operating Voltage | The lowest voltage sufficient for stable operation under specified conditions. It is not a sensor Minimum or simply the current load voltage. The identified boundary needs margin and repeat testing (9.3.1). |
| Steady state | Steady-state Load | An established load condition useful for comparable measurements. It does not fully describe applying or removing a load, or exiting power-saving states. |
| Transient / Overshoot | Load Transient / Voltage Overshoot | A transient event when the load changes, with a possible brief voltage overshoot. A failure during a transition does not, by itself, prove that overshoot was the cause. |
| Effective Clocks | Core Effective Clocks | Effective clock speed over a measurement interval, accounting for core activity and sleep. Compare it with the regular clock speed, utilization, and the result of the same test. |
| Clock stretching | Clock Stretching | Reduced effective work execution despite an apparently high clock speed. A gap between Core Clocks and Effective Clocks alone does not prove CEP intervention, especially at idle. |
| Limit Reasons | Performance Limit Reasons | Flags indicating why operation is being limited. They help distinguish power, current, and temperature limits; a recorded maximum flag does not always describe the current moment under load. |
| WHEA | Windows Hardware Error Architecture | Windows hardware events: System → WHEA-Logger, during the run (5.3). Examine source/error type. WHEA does not automatically identify CPU cores; no events does not prove stability. |
| y-cruncher | Component Stress Tester | BKT, BBP, SFTv4, and SVT supplement CPU/cache validation; VT3 uses a large working set. Components and the run sequence are covered in detail in 5.4. |
| AVX / AVX2 | Advanced Vector Extensions / Advanced Vector Extensions 2 | Vector instruction sets that change the nature of the computational load. Passing a heavy AVX test does not validate stability at upper clock speeds in light or lightly threaded workloads. |
| Microcode | Processor Microcode | Internal fixes to processor behavior, distributed through BIOS among other channels. Record the version with the profile; repeat key checks after an update. |
| Cold boot / Sleep-wake | Cold Boot / Sleep and Wake | Starting from a powered-off state and transitioning from sleep to wake. Check that settings are applied consistently and that there are no hangs, reboots, or new errors after power-state changes. |
| Daily envelope | Daily-use Operating Envelope | The combination of allowed clock speeds, voltages, power, current, and temperatures for daily workloads. Assess it together with cooling, noise, and actual performance. |
| DC verification | DC Load-line Verification | Checking the applied DC against the LLC table (3.2) and checking the model in comparable operating modes (5.2). A single VID/VOUT match does not prove the entire configuration is correct. |
| Energy / task | Energy per Completed Task | Energy per correctly completed instance of the same task. Compare it alongside execution time and conditions; lower power due to reduced performance does not prove better efficiency. |
| Current / Minimum | Current / Minimum / Maximum | Current, lowest and highest readings since statistics were reset. Minima in different rows need not be simultaneous; without a reset they may come from idle (9.3.1). |
| IMC / RAM / DRAM | Integrated Memory Controller / Random Access Memory / Dynamic RAM | IMC is the CPU integrated memory controller; RAM is system memory, and DRAM is its dynamic type. An error in a combined CPU and memory test does not by itself identify the faulty component. |
DOCUMENTATION CONSULTED: explanations by the HWiNFO author; software and Windows documentation; Intel specifications and explanations. HWiNFO: Effective Clock, y-cruncher, Intel Core Ultra 200S / DLVR 31