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    DDR5 manualVERSION 4.04 · 16.10.2026

    CHANGELOG

    A concise history of project revisions.

    3.01 - 3.04

    3.01

    • First public English edition.

    3.02

    • P. 4. Reworked the introduction: approach, limits of the evidence, and the Read Timing Centering 2D example. My personal preference is Enabled.
    • PP. 31, 82. Clarified the limits of calculating tREFIx9 directly; retained Auto.
    • PP. 47-48, 77, 85. Specified the conditions for converting RTL/QCLK to nanoseconds.
    • PP. 26-27, 81. Distinguished calculated tRC from the actual ACT-to-ACT interval.
    • P. 43. Clarified the role of BIOS/MRC after loading XMP II.
    • P. 53. Distinguished a temperature plateau from sufficient y-cruncher validation.
    • P. 75. Clarified the description of recorded WHEA events.
    • P. 11. Added Ring and a qualification to the IMC diagram, clarified DDR5 channels and subchannels.
    • P. 42. Revised the voltage and cooling table. Clarified that there is no single official safe range for manual overclocking; retained my values.
    • P. 34. Corrected tXS(min) for monolithic DDR5 (DDR5 devices with one DRAM die per package) to tRFC1; separately specified tXS_DLL = tDLLK for commands that require the DLL.
    • P. 37. Clarified the purpose of CKD PLL Bypass: compatibility and diagnostics.
    • P. 56. Clarified on-die ECC: ECS counters are available through registers where supported by the platform; they are not a system ECC report. Added the SK hynix primary source.
    • PP. 69, 89. Updated current AIDA64 downloads to 8.40.5000 and the documentation review date. Retained the historical 8.35 results.
    • P. 73. Added milliseconds to the P1 FPS = 1000 / P99 frame time formula.
    • In revision 3.02, pp. 88-101. Added Chapter 13: the complete catalog of DDR5 kits and desktop memory modules
    • Throughout. Completed a technical audit and another editorial review, making only justified, targeted changes. Checked formulas, tables, sources, and consistency of the methodology.
    • PP. 77-87. Reviewed and expanded the glossary: refined definitions and added terms used in the manual and catalog.

    3.03

    • P. 90. Moved the complete catalog of DDR5 kits and desktop memory modules to a separate PDF. Chapter 13 contains a download link.

    3.04

    • PP. 4, 69, 85. Corrected the Intel FSP links for Read Timing Centering 2D. Updated PresentMon downloads to 2.6.0 and added the .NET 10 Desktop Runtime x64 requirement for CapFrameX.
    • PP. 24, 78, 83. Added Section 2.13 on two-slot Maxsun Z690-Z890 boards: a model classifier, review results and announced boards. Expanded the glossary.

    4.00

    • P. 53. Clarified the y-cruncher chapter: what the tests check, how to compare results and what to do after an error. Set the time per component to 60-120 seconds.
    • P. 76. Added Chapter 10, “Formulas”, with timing relationships, tFAW for 1/2 KB, a tRFCpb estimate, Power Down, tREFI, and RTL; established tWR=48 as the practical standard.
    • PP. 30, 32-34. Explained WR/WTR calculation differences between utilities, tCKE/tXP with PD=0, and OREF_RI; clarified the limits of the simplified tRFCpb estimate.
    • PP. 69, 89. Updated HWiNFO, Cinebench, and CapFrameX information; corrected the EVGA link.
    • PP. 10, 26, 31, 33, 42, 76. Clarified bandwidth units, tREFI, refresh modes, dr/dd applicability, and the stability requirement when reducing voltage.
    • P. 50. Rechecked the ODT table: clarified Z790/Z890 test conditions, RON order and DIMM Fit Pro results; removed unverified high-frequency presets.
    • Corrected minor issues and refined some wording throughout the document.

    4.01

    • P. 15. Added a PMIC chapter covering DDR5 power, newer designs and overclocking capabilities. The table lists nine kits with verified chip markings, including 2 × 24, 2 × 48 and 2 × 64 GB.
    • P. 18–19. Added a 2R + DS diagram showing two ranks and ICs on both sides. Clarified the organization of 32 and 48 GB modules.
    • P. 22. Expanded the operating-point table with 2 × 24, 2 × 48 and 2 × 64 GB kits. Clarified IC revisions and the practical 7200 MT/s target for 2 × 32 and 2 × 48 GB.
    • P. 91–96. Updated the glossary: SKU, PMIC5120, module power and High DRAM Voltage mode.
    • Removed repetitive explanations and qualifications throughout the manual, while preserving calculation conditions, technical limits and warnings about real risks.

    4.02

    • P. 73. Clarified how to compare bandwidth, latency and in-game results.
    • P. 74. Explained Hardware Prefetcher and added a note on its effect on Read/Write/Copy.
    • P. 79, 81–82, 103–105. Checked software versions and links throughout the manual; updated details and download URLs.

    4.03

    4.04